Crypto++  5.6.5
Free C++ class library of cryptographic schemes
cpu.h
Go to the documentation of this file.
1 // cpu.h - written and placed in the public domain by Wei Dai
2 
3 //! \file cpu.h
4 //! \brief Functions for CPU features and intrinsics
5 //! \details The functions are used in X86/X32/X64 and NEON code paths
6 
7 #ifndef CRYPTOPP_CPU_H
8 #define CRYPTOPP_CPU_H
9 
10 #include "config.h"
11 
12 // Issue 340
13 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
14 # pragma GCC diagnostic push
15 # pragma GCC diagnostic ignored "-Wconversion"
16 # pragma GCC diagnostic ignored "-Wsign-conversion"
17 #endif
18 
19 // ARM32/ARM64 Headers
20 #if (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
21 # if defined(__GNUC__)
22 # include <stdint.h>
23 # endif
24 # if CRYPTOPP_BOOL_NEON_INTRINSICS_AVAILABLE || defined(__ARM_NEON)
25 # include <arm_neon.h>
26 # endif
27 # if (CRYPTOPP_BOOL_ARM_CRYPTO_INTRINSICS_AVAILABLE || CRYPTOPP_BOOL_ARM_CRC32_INTRINSICS_AVAILABLE) || defined(__ARM_ACLE)
28 # include <arm_acle.h>
29 # endif
30 #endif // ARM32 and ARM64 Headers
31 
32 // X86/X64/X32 Headers
33 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
34 
35 // GCC X86 super-include
36 #if (CRYPTOPP_GCC_VERSION >= 40800)
37 # include <x86intrin.h>
38 #endif
39 #if (CRYPTOPP_MSC_VERSION >= 1400)
40 # include <intrin.h>
41 #endif
42 
43 // Baseline include
44 #if CRYPTOPP_BOOL_SSE2_INTRINSICS_AVAILABLE
45 # include <emmintrin.h> // __m64, __m128i, _mm_set_epi64x
46 #endif
47 #if CRYPTOPP_BOOL_SSSE3_ASM_AVAILABLE
48 # include <tmmintrin.h> // _mm_shuffle_pi8, _mm_shuffle_epi8
49 #endif // tmmintrin.h
50 #if CRYPTOPP_BOOL_SSE4_INTRINSICS_AVAILABLE
51 # include <smmintrin.h> // _mm_blend_epi16
52 # include <nmmintrin.h> // _mm_crc32_u{8|16|32}
53 #endif // smmintrin.h
54 #if CRYPTOPP_BOOL_AESNI_INTRINSICS_AVAILABLE
55 # include <wmmintrin.h> // aesenc, aesdec, etc
56 #endif // wmmintrin.h
57 #if CRYPTOPP_BOOL_SSE_SHA_INTRINSICS_AVAILABLE
58 # include <immintrin.h> // RDRAND, RDSEED, AVX, SHA
59 #endif // immintrin.h
60 #endif // X86/X64/X32 Headers
61 
62 // Applies to both X86/X32/X64 and ARM32/ARM64. And we've got MIPS devices on the way.
63 #if defined(_MSC_VER) || defined(__BORLANDC__)
64 # define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
65 #else
66 # define CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
67 #endif
68 
69 // Applies to both X86/X32/X64 and ARM32/ARM64
70 #if defined(CRYPTOPP_LLVM_CLANG_VERSION) || defined(CRYPTOPP_APPLE_CLANG_VERSION) || defined(CRYPTOPP_CLANG_INTEGRATED_ASSEMBLER)
71  #define NEW_LINE "\n"
72  #define INTEL_PREFIX ".intel_syntax;"
73  #define INTEL_NOPREFIX ".intel_syntax;"
74  #define ATT_PREFIX ".att_syntax;"
75  #define ATT_NOPREFIX ".att_syntax;"
76 #elif defined(__GNUC__)
77  #define NEW_LINE
78  #define INTEL_PREFIX ".intel_syntax prefix;"
79  #define INTEL_NOPREFIX ".intel_syntax noprefix;"
80  #define ATT_PREFIX ".att_syntax prefix;"
81  #define ATT_NOPREFIX ".att_syntax noprefix;"
82 #else
83  #define NEW_LINE
84  #define INTEL_PREFIX
85  #define INTEL_NOPREFIX
86  #define ATT_PREFIX
87  #define ATT_NOPREFIX
88 #endif
89 
90 #ifdef CRYPTOPP_GENERATE_X64_MASM
91 
92 #define CRYPTOPP_X86_ASM_AVAILABLE
93 #define CRYPTOPP_BOOL_X64 1
94 #define CRYPTOPP_BOOL_SSE2_ASM_AVAILABLE 1
95 #define NAMESPACE_END
96 
97 #else
98 
99 NAMESPACE_BEGIN(CryptoPP)
100 
101 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
102 
103 #define CRYPTOPP_CPUID_AVAILABLE
104 
105 // Hide from Doxygen
106 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
107 // These should not be used directly
108 extern CRYPTOPP_DLL bool g_x86DetectionDone;
109 extern CRYPTOPP_DLL bool g_hasMMX;
110 extern CRYPTOPP_DLL bool g_hasISSE;
111 extern CRYPTOPP_DLL bool g_hasSSE2;
112 extern CRYPTOPP_DLL bool g_hasSSSE3;
113 extern CRYPTOPP_DLL bool g_hasSSE4;
114 extern CRYPTOPP_DLL bool g_hasAESNI;
115 extern CRYPTOPP_DLL bool g_hasCLMUL;
116 extern CRYPTOPP_DLL bool g_hasSHA;
117 extern CRYPTOPP_DLL bool g_isP4;
118 extern CRYPTOPP_DLL bool g_hasRDRAND;
119 extern CRYPTOPP_DLL bool g_hasRDSEED;
120 extern CRYPTOPP_DLL bool g_hasPadlockRNG;
121 extern CRYPTOPP_DLL bool g_hasPadlockACE;
122 extern CRYPTOPP_DLL bool g_hasPadlockACE2;
123 extern CRYPTOPP_DLL bool g_hasPadlockPHE;
124 extern CRYPTOPP_DLL bool g_hasPadlockPMM;
125 extern CRYPTOPP_DLL word32 g_cacheLineSize;
126 
127 CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
128 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 input, word32 output[4]);
129 #endif // CRYPTOPP_DOXYGEN_PROCESSING
130 
131 //! \brief Determines MMX availability
132 //! \returns true if MMX is determined to be available, false otherwise
133 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
134 //! the function always returns true for the platform.
135 inline bool HasMMX()
136 {
137 #if CRYPTOPP_BOOL_X64
138  return true;
139 #else
140  if (!g_x86DetectionDone)
141  DetectX86Features();
142  return g_hasMMX;
143 #endif
144 }
145 
146 //! \brief Determines SSE availability
147 //! \returns true if SSE is determined to be available, false otherwise
148 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
149 //! the function always returns true for the platform.
150 inline bool HasISSE()
151 {
152 #if CRYPTOPP_BOOL_X64
153  return true;
154 #else
155  if (!g_x86DetectionDone)
156  DetectX86Features();
157  return g_hasISSE;
158 #endif
159 }
160 
161 //! \brief Determines SSE2 availability
162 //! \returns true if SSE2 is determined to be available, false otherwise
163 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
164 //! the function always returns true for the platform.
165 inline bool HasSSE2()
166 {
167 #if CRYPTOPP_BOOL_X64
168  return true;
169 #else
170  if (!g_x86DetectionDone)
171  DetectX86Features();
172  return g_hasSSE2;
173 #endif
174 }
175 
176 //! \brief Determines SSSE3 availability
177 //! \returns true if SSSE3 is determined to be available, false otherwise
178 //! \details HasSSSE3() is a runtime check performed using CPUID
179 //! \note Some Clang compilers incorrectly omit SSSE3 even though its native to the processor.
180 inline bool HasSSSE3()
181 {
182  if (!g_x86DetectionDone)
183  DetectX86Features();
184  return g_hasSSSE3;
185 }
186 
187 //! \brief Determines SSE4 availability
188 //! \returns true if SSE4.1 and SSE4.2 are determined to be available, false otherwise
189 //! \details HasSSE4() is a runtime check performed using CPUID which requires both SSE4.1 and SSE4.2
190 inline bool HasSSE4()
191 {
192  if (!g_x86DetectionDone)
193  DetectX86Features();
194  return g_hasSSE4;
195 }
196 
197 //! \brief Determines AES-NI availability
198 //! \returns true if AES-NI is determined to be available, false otherwise
199 //! \details HasAESNI() is a runtime check performed using CPUID
200 inline bool HasAESNI()
201 {
202  if (!g_x86DetectionDone)
203  DetectX86Features();
204  return g_hasAESNI;
205 }
206 
207 //! \brief Determines Carryless Multiply availability
208 //! \returns true if pclmulqdq is determined to be available, false otherwise
209 //! \details HasCLMUL() is a runtime check performed using CPUID
210 inline bool HasCLMUL()
211 {
212  if (!g_x86DetectionDone)
213  DetectX86Features();
214  return g_hasCLMUL;
215 }
216 
217 //! \brief Determines SHA availability
218 //! \returns true if SHA is determined to be available, false otherwise
219 //! \details HasSHA() is a runtime check performed using CPUID
220 inline bool HasSHA()
221 {
222  if (!g_x86DetectionDone)
223  DetectX86Features();
224  return g_hasSHA;
225 }
226 
227 //! \brief Determines if the CPU is an Intel P4
228 //! \returns true if the CPU is a P4, false otherwise
229 //! \details IsP4() is a runtime check performed using CPUID
230 inline bool IsP4()
231 {
232  if (!g_x86DetectionDone)
233  DetectX86Features();
234  return g_isP4;
235 }
236 
237 //! \brief Determines RDRAND availability
238 //! \returns true if RDRAND is determined to be available, false otherwise
239 //! \details HasRDRAND() is a runtime check performed using CPUID
240 inline bool HasRDRAND()
241 {
242  if (!g_x86DetectionDone)
243  DetectX86Features();
244  return g_hasRDRAND;
245 }
246 
247 //! \brief Determines RDSEED availability
248 //! \returns true if RDSEED is determined to be available, false otherwise
249 //! \details HasRDSEED() is a runtime check performed using CPUID
250 inline bool HasRDSEED()
251 {
252  if (!g_x86DetectionDone)
253  DetectX86Features();
254  return g_hasRDSEED;
255 }
256 
257 //! \brief Determines Padlock RNG availability
258 //! \returns true if VIA Padlock RNG is determined to be available, false otherwise
259 //! \details HasPadlockRNG() is a runtime check performed using CPUID
260 inline bool HasPadlockRNG()
261 {
262  if (!g_x86DetectionDone)
263  DetectX86Features();
264  return g_hasPadlockRNG;
265 }
266 
267 //! \brief Determines Padlock ACE availability
268 //! \returns true if VIA Padlock ACE is determined to be available, false otherwise
269 //! \details HasPadlockACE() is a runtime check performed using CPUID
270 inline bool HasPadlockACE()
271 {
272  if (!g_x86DetectionDone)
273  DetectX86Features();
274  return g_hasPadlockACE;
275 }
276 
277 //! \brief Determines Padlock ACE2 availability
278 //! \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
279 //! \details HasPadlockACE2() is a runtime check performed using CPUID
280 inline bool HasPadlockACE2()
281 {
282  if (!g_x86DetectionDone)
283  DetectX86Features();
284  return g_hasPadlockACE2;
285 }
286 
287 //! \brief Determines Padlock PHE availability
288 //! \returns true if VIA Padlock PHE is determined to be available, false otherwise
289 //! \details HasPadlockPHE() is a runtime check performed using CPUID
290 inline bool HasPadlockPHE()
291 {
292  if (!g_x86DetectionDone)
293  DetectX86Features();
294  return g_hasPadlockPHE;
295 }
296 
297 //! \brief Determines Padlock PMM availability
298 //! \returns true if VIA Padlock PMM is determined to be available, false otherwise
299 //! \details HasPadlockPMM() is a runtime check performed using CPUID
300 inline bool HasPadlockPMM()
301 {
302  if (!g_x86DetectionDone)
303  DetectX86Features();
304  return g_hasPadlockPMM;
305 }
306 
307 //! \brief Provides the cache line size
308 //! \returns lower bound on the size of a cache line in bytes, if available
309 //! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
310 //! is available. If the value is not available at runtime, then 32 is returned for a 32-bit
311 //! processor and 64 is returned for a 64-bit processor.
312 //! \details x86/x32/x64 uses CPUID to determine the value and its usually accurate. The ARM
313 //! processor equivalent is a privileged instruction, so a compile time value is returned.
314 inline int GetCacheLineSize()
315 {
316  if (!g_x86DetectionDone)
317  DetectX86Features();
318  return g_cacheLineSize;
319 }
320 
321 #elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
322 
323 extern bool g_ArmDetectionDone;
324 extern bool g_hasNEON, g_hasPMULL, g_hasCRC32, g_hasAES, g_hasSHA1, g_hasSHA2;
325 void CRYPTOPP_API DetectArmFeatures();
326 
327 //! \brief Determine if an ARM processor has Advanced SIMD available
328 //! \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
329 //! \details Advanced SIMD instructions are available under Aarch64 (ARM-64) and Aarch32 (ARM-32).
330 //! \details Runtime support requires compile time support. When compiling with GCC, you may
331 //! need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>
332 //! (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.
333 inline bool HasNEON()
334 {
335  if (!g_ArmDetectionDone)
336  DetectArmFeatures();
337  return g_hasNEON;
338 }
339 
340 //! \brief Determine if an ARM processor provides Polynomial Multiplication (long)
341 //! \returns true if the hardware is capable of polynomial multiplications at runtime, false otherwise.
342 //! \details The multiplication instructions are available under Aarch64 (ARM-64) and Aarch32 (ARM-32).
343 //! \details Runtime support requires compile time support. When compiling with GCC, you may
344 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
345 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
346 inline bool HasPMULL()
347 {
348  if (!g_ArmDetectionDone)
349  DetectArmFeatures();
350  return g_hasPMULL;
351 }
352 
353 //! \brief Determine if an ARM processor has CRC32 available
354 //! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
355 //! \details CRC32 instructions provide access to the processor's CRC32 and CRC32-C intructions.
356 //! They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and available under Aarch64
357 //! (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an AArch32 execution environment).
358 //! \details Runtime support requires compile time support. When compiling with GCC, you may
359 //! need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires
360 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.
361 inline bool HasCRC32()
362 {
363  if (!g_ArmDetectionDone)
364  DetectArmFeatures();
365  return g_hasCRC32;
366 }
367 
368 //! \brief Determine if an ARM processor has AES available
369 //! \returns true if the hardware is capable of AES at runtime, false otherwise.
370 //! \details AES is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
371 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
372 //! AArch32 execution environment).
373 //! \details Runtime support requires compile time support. When compiling with GCC, you may
374 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
375 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
376 inline bool HasAES()
377 {
378  if (!g_ArmDetectionDone)
379  DetectArmFeatures();
380  return g_hasAES;
381 }
382 
383 //! \brief Determine if an ARM processor has SHA1 available
384 //! \returns true if the hardware is capable of SHA1 at runtime, false otherwise.
385 //! \details SHA1 is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
386 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
387 //! AArch32 execution environment).
388 //! \details Runtime support requires compile time support. When compiling with GCC, you may
389 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
390 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
391 inline bool HasSHA1()
392 {
393  if (!g_ArmDetectionDone)
394  DetectArmFeatures();
395  return g_hasSHA1;
396 }
397 
398 //! \brief Determine if an ARM processor has SHA2 available
399 //! \returns true if the hardware is capable of SHA2 at runtime, false otherwise.
400 //! \details SHA2 is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
401 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
402 //! AArch32 execution environment).
403 //! \details Runtime support requires compile time support. When compiling with GCC, you may
404 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
405 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
406 inline bool HasSHA2()
407 {
408  if (!g_ArmDetectionDone)
409  DetectArmFeatures();
410  return g_hasSHA2;
411 }
412 
413 //! \brief Provides the cache line size at runtime
414 //! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
415 //! \details GetCacheLineSize() provides is an estimate using CRYPTOPP_L1_CACHE_LINE_SIZE.
416 //! The runtime instructions to query the processor are privileged.
417 inline int GetCacheLineSize()
418 {
419  return CRYPTOPP_L1_CACHE_LINE_SIZE;
420 }
421 
422 #else
423 
424 inline int GetCacheLineSize()
425 {
426  return CRYPTOPP_L1_CACHE_LINE_SIZE;
427 }
428 
429 #endif // X86/X32/X64 and ARM
430 
431 #endif
432 
433 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
434 
435 #ifdef CRYPTOPP_GENERATE_X64_MASM
436  #define AS1(x) x*newline*
437  #define AS2(x, y) x, y*newline*
438  #define AS3(x, y, z) x, y, z*newline*
439  #define ASS(x, y, a, b, c, d) x, y, a*64+b*16+c*4+d*newline*
440  #define ASL(x) label##x:*newline*
441  #define ASJ(x, y, z) x label##y*newline*
442  #define ASC(x, y) x label##y*newline*
443  #define AS_HEX(y) 0##y##h
444 #elif defined(_MSC_VER) || defined(__BORLANDC__)
445  #define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
446  #define AS1(x) __asm {x}
447  #define AS2(x, y) __asm {x, y}
448  #define AS3(x, y, z) __asm {x, y, z}
449  #define ASS(x, y, a, b, c, d) __asm {x, y, (a)*64+(b)*16+(c)*4+(d)}
450  #define ASL(x) __asm {label##x:}
451  #define ASJ(x, y, z) __asm {x label##y}
452  #define ASC(x, y) __asm {x label##y}
453  #define CRYPTOPP_NAKED __declspec(naked)
454  #define AS_HEX(y) 0x##y
455 #else
456  #define CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
457 
458  // define these in two steps to allow arguments to be expanded
459  #define GNU_AS1(x) #x ";" NEW_LINE
460  #define GNU_AS2(x, y) #x ", " #y ";" NEW_LINE
461  #define GNU_AS3(x, y, z) #x ", " #y ", " #z ";" NEW_LINE
462  #define GNU_ASL(x) "\n" #x ":" NEW_LINE
463  #define GNU_ASJ(x, y, z) #x " " #y #z ";" NEW_LINE
464  #define AS1(x) GNU_AS1(x)
465  #define AS2(x, y) GNU_AS2(x, y)
466  #define AS3(x, y, z) GNU_AS3(x, y, z)
467  #define ASS(x, y, a, b, c, d) #x ", " #y ", " #a "*64+" #b "*16+" #c "*4+" #d ";"
468  #define ASL(x) GNU_ASL(x)
469  #define ASJ(x, y, z) GNU_ASJ(x, y, z)
470  #define ASC(x, y) #x " " #y ";"
471  #define CRYPTOPP_NAKED
472  #define AS_HEX(y) 0x##y
473 #endif
474 
475 #define IF0(y)
476 #define IF1(y) y
477 
478 #ifdef CRYPTOPP_GENERATE_X64_MASM
479 #define ASM_MOD(x, y) ((x) MOD (y))
480 #define XMMWORD_PTR XMMWORD PTR
481 #else
482 // GNU assembler doesn't seem to have mod operator
483 #define ASM_MOD(x, y) ((x)-((x)/(y))*(y))
484 // GAS 2.15 doesn't support XMMWORD PTR. it seems necessary only for MASM
485 #define XMMWORD_PTR
486 #endif
487 
488 #if CRYPTOPP_BOOL_X86
489  #define AS_REG_1 ecx
490  #define AS_REG_2 edx
491  #define AS_REG_3 esi
492  #define AS_REG_4 edi
493  #define AS_REG_5 eax
494  #define AS_REG_6 ebx
495  #define AS_REG_7 ebp
496  #define AS_REG_1d ecx
497  #define AS_REG_2d edx
498  #define AS_REG_3d esi
499  #define AS_REG_4d edi
500  #define AS_REG_5d eax
501  #define AS_REG_6d ebx
502  #define AS_REG_7d ebp
503  #define WORD_SZ 4
504  #define WORD_REG(x) e##x
505  #define WORD_PTR DWORD PTR
506  #define AS_PUSH_IF86(x) AS1(push e##x)
507  #define AS_POP_IF86(x) AS1(pop e##x)
508  #define AS_JCXZ jecxz
509 #elif CRYPTOPP_BOOL_X32
510  #define AS_REG_1 ecx
511  #define AS_REG_2 edx
512  #define AS_REG_3 r8d
513  #define AS_REG_4 r9d
514  #define AS_REG_5 eax
515  #define AS_REG_6 r10d
516  #define AS_REG_7 r11d
517  #define AS_REG_1d ecx
518  #define AS_REG_2d edx
519  #define AS_REG_3d r8d
520  #define AS_REG_4d r9d
521  #define AS_REG_5d eax
522  #define AS_REG_6d r10d
523  #define AS_REG_7d r11d
524  #define WORD_SZ 4
525  #define WORD_REG(x) e##x
526  #define WORD_PTR DWORD PTR
527  #define AS_PUSH_IF86(x) AS1(push r##x)
528  #define AS_POP_IF86(x) AS1(pop r##x)
529  #define AS_JCXZ jecxz
530 #elif CRYPTOPP_BOOL_X64
531  #ifdef CRYPTOPP_GENERATE_X64_MASM
532  #define AS_REG_1 rcx
533  #define AS_REG_2 rdx
534  #define AS_REG_3 r8
535  #define AS_REG_4 r9
536  #define AS_REG_5 rax
537  #define AS_REG_6 r10
538  #define AS_REG_7 r11
539  #define AS_REG_1d ecx
540  #define AS_REG_2d edx
541  #define AS_REG_3d r8d
542  #define AS_REG_4d r9d
543  #define AS_REG_5d eax
544  #define AS_REG_6d r10d
545  #define AS_REG_7d r11d
546  #else
547  #define AS_REG_1 rdi
548  #define AS_REG_2 rsi
549  #define AS_REG_3 rdx
550  #define AS_REG_4 rcx
551  #define AS_REG_5 r8
552  #define AS_REG_6 r9
553  #define AS_REG_7 r10
554  #define AS_REG_1d edi
555  #define AS_REG_2d esi
556  #define AS_REG_3d edx
557  #define AS_REG_4d ecx
558  #define AS_REG_5d r8d
559  #define AS_REG_6d r9d
560  #define AS_REG_7d r10d
561  #endif
562  #define WORD_SZ 8
563  #define WORD_REG(x) r##x
564  #define WORD_PTR QWORD PTR
565  #define AS_PUSH_IF86(x)
566  #define AS_POP_IF86(x)
567  #define AS_JCXZ jrcxz
568 #endif
569 
570 // helper macro for stream cipher output
571 #define AS_XMM_OUTPUT4(labelPrefix, inputPtr, outputPtr, x0, x1, x2, x3, t, p0, p1, p2, p3, increment)\
572  AS2( test inputPtr, inputPtr)\
573  ASC( jz, labelPrefix##3)\
574  AS2( test inputPtr, 15)\
575  ASC( jnz, labelPrefix##7)\
576  AS2( pxor xmm##x0, [inputPtr+p0*16])\
577  AS2( pxor xmm##x1, [inputPtr+p1*16])\
578  AS2( pxor xmm##x2, [inputPtr+p2*16])\
579  AS2( pxor xmm##x3, [inputPtr+p3*16])\
580  AS2( add inputPtr, increment*16)\
581  ASC( jmp, labelPrefix##3)\
582  ASL(labelPrefix##7)\
583  AS2( movdqu xmm##t, [inputPtr+p0*16])\
584  AS2( pxor xmm##x0, xmm##t)\
585  AS2( movdqu xmm##t, [inputPtr+p1*16])\
586  AS2( pxor xmm##x1, xmm##t)\
587  AS2( movdqu xmm##t, [inputPtr+p2*16])\
588  AS2( pxor xmm##x2, xmm##t)\
589  AS2( movdqu xmm##t, [inputPtr+p3*16])\
590  AS2( pxor xmm##x3, xmm##t)\
591  AS2( add inputPtr, increment*16)\
592  ASL(labelPrefix##3)\
593  AS2( test outputPtr, 15)\
594  ASC( jnz, labelPrefix##8)\
595  AS2( movdqa [outputPtr+p0*16], xmm##x0)\
596  AS2( movdqa [outputPtr+p1*16], xmm##x1)\
597  AS2( movdqa [outputPtr+p2*16], xmm##x2)\
598  AS2( movdqa [outputPtr+p3*16], xmm##x3)\
599  ASC( jmp, labelPrefix##9)\
600  ASL(labelPrefix##8)\
601  AS2( movdqu [outputPtr+p0*16], xmm##x0)\
602  AS2( movdqu [outputPtr+p1*16], xmm##x1)\
603  AS2( movdqu [outputPtr+p2*16], xmm##x2)\
604  AS2( movdqu [outputPtr+p3*16], xmm##x3)\
605  ASL(labelPrefix##9)\
606  AS2( add outputPtr, increment*16)
607 
608 #endif // X86/X32/X64
609 
610 NAMESPACE_END
611 
612 // Issue 340
613 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
614 # pragma GCC diagnostic pop
615 #endif
616 
617 #endif // CRYPTOPP_CPU_H
bool HasSHA()
Determines SHA availability.
Definition: cpu.h:220
bool HasISSE()
Determines SSE availability.
Definition: cpu.h:150
bool HasSSE4()
Determines SSE4 availability.
Definition: cpu.h:190
bool HasSSSE3()
Determines SSSE3 availability.
Definition: cpu.h:180
bool HasPadlockRNG()
Determines Padlock RNG availability.
Definition: cpu.h:260
bool IsP4()
Determines if the CPU is an Intel P4.
Definition: cpu.h:230
Library configuration file.
int GetCacheLineSize()
Provides the cache line size.
Definition: cpu.h:314
bool HasRDRAND()
Determines RDRAND availability.
Definition: cpu.h:240
bool HasRDSEED()
Determines RDSEED availability.
Definition: cpu.h:250
bool HasCLMUL()
Determines Carryless Multiply availability.
Definition: cpu.h:210
bool HasPadlockACE2()
Determines Padlock ACE2 availability.
Definition: cpu.h:280
bool HasPadlockPHE()
Determines Padlock PHE availability.
Definition: cpu.h:290
bool HasPadlockPMM()
Determines Padlock PMM availability.
Definition: cpu.h:300
bool HasAESNI()
Determines AES-NI availability.
Definition: cpu.h:200
bool HasSSE2()
Determines SSE2 availability.
Definition: cpu.h:165
bool HasMMX()
Determines MMX availability.
Definition: cpu.h:135
Crypto++ library namespace.
bool HasPadlockACE()
Determines Padlock ACE availability.
Definition: cpu.h:270