Crypto++  5.6.5
Free C++ class library of cryptographic schemes
cpu.h
Go to the documentation of this file.
1 // cpu.h - originally written and placed in the public domain by Wei Dai
2 // updated for ARM by Jeffrey Walton
3 
4 //! \file cpu.h
5 //! \brief Functions for CPU features and intrinsics
6 //! \details The functions are used in X86/X32/X64 and ARM code paths
7 
8 #ifndef CRYPTOPP_CPU_H
9 #define CRYPTOPP_CPU_H
10 
11 #include "config.h"
12 
13 // Issue 340
14 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
15 # pragma GCC diagnostic push
16 # pragma GCC diagnostic ignored "-Wconversion"
17 # pragma GCC diagnostic ignored "-Wsign-conversion"
18 #endif
19 
20 // ARM32 and ARM64 Headers
21 #if (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
22 # if defined(__GNUC__)
23 # include <stdint.h>
24 # endif
25 # if defined(__ARM_NEON) || defined(_MSC_VER)
26 # include <arm_neon.h>
27 # endif
28 # if defined(__GNUC__) && !defined(__apple_build_version__)
29 # if defined(__ARM_ACLE) || defined(__ARM_FEATURE_CRC32) || defined(__ARM_FEATURE_CRYPTO)
30 # include <arm_acle.h>
31 # endif
32 # endif
33 #endif // ARM32 and ARM64 Headers
34 
35 // Used when supplying ASM due to missing intrinsics
36 #if defined(__clang__)
37 # define GCC_INLINE inline
38 # define GCC_INLINE_ATTRIB __attribute__((__gnu_inline__, __always_inline__))
39 #elif (CRYPTOPP_GCC_VERSION >= 30300) || defined(__INTEL_COMPILER)
40 # define GCC_INLINE __inline
41 # define GCC_INLINE_ATTRIB __attribute__((__gnu_inline__, __always_inline__, __artificial__))
42 #else
43 # define GCC_INLINE inline
44 # define GCC_INLINE_ATTRIB
45 # endif
46 
47 // X86/X64/X32 Headers
48 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
49 
50 // GCC X86 super-include
51 #if (CRYPTOPP_GCC_VERSION >= 40800)
52 # include <x86intrin.h>
53 #endif
54 #if (CRYPTOPP_MSC_VERSION >= 1400)
55 # include <intrin.h>
56 #endif
57 
58 // Baseline include
59 #if CRYPTOPP_BOOL_SSE2_INTRINSICS_AVAILABLE
60 # include <emmintrin.h> // __m64, __m128i, _mm_set_epi64x
61 #endif
62 #if CRYPTOPP_BOOL_SSSE3_INTRINSICS_AVAILABLE
63 # include <tmmintrin.h> // _mm_shuffle_pi8, _mm_shuffle_epi8
64 #endif // tmmintrin.h
65 #if CRYPTOPP_BOOL_SSE4_INTRINSICS_AVAILABLE
66 # include <smmintrin.h> // _mm_blend_epi16
67 # include <nmmintrin.h> // _mm_crc32_u{8|16|32}
68 #endif // smmintrin.h
69 #if CRYPTOPP_BOOL_AESNI_INTRINSICS_AVAILABLE
70 # include <wmmintrin.h> // aesenc, aesdec, etc
71 #endif // wmmintrin.h
72 #if CRYPTOPP_BOOL_SSE_SHA_INTRINSICS_AVAILABLE
73 # include <immintrin.h> // RDRAND, RDSEED, AVX, SHA
74 #endif // immintrin.h
75 #endif // X86/X64/X32 Headers
76 
77 // Applies to both X86/X32/X64 and ARM32/ARM64. And we've got MIPS devices on the way.
78 #if defined(_MSC_VER) || defined(__BORLANDC__)
79 # define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
80 #else
81 # define CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
82 #endif
83 
84 // Applies to both X86/X32/X64 and ARM32/ARM64
85 #if defined(CRYPTOPP_LLVM_CLANG_VERSION) || defined(CRYPTOPP_APPLE_CLANG_VERSION) || defined(CRYPTOPP_CLANG_INTEGRATED_ASSEMBLER)
86  #define NEW_LINE "\n"
87  #define INTEL_PREFIX ".intel_syntax;"
88  #define INTEL_NOPREFIX ".intel_syntax;"
89  #define ATT_PREFIX ".att_syntax;"
90  #define ATT_NOPREFIX ".att_syntax;"
91 #elif defined(__GNUC__)
92  #define NEW_LINE
93  #define INTEL_PREFIX ".intel_syntax prefix;"
94  #define INTEL_NOPREFIX ".intel_syntax noprefix;"
95  #define ATT_PREFIX ".att_syntax prefix;"
96  #define ATT_NOPREFIX ".att_syntax noprefix;"
97 #else
98  #define NEW_LINE
99  #define INTEL_PREFIX
100  #define INTEL_NOPREFIX
101  #define ATT_PREFIX
102  #define ATT_NOPREFIX
103 #endif
104 
105 #ifdef CRYPTOPP_GENERATE_X64_MASM
106 
107 #define CRYPTOPP_X86_ASM_AVAILABLE
108 #define CRYPTOPP_BOOL_X64 1
109 #define CRYPTOPP_BOOL_SSE2_ASM_AVAILABLE 1
110 #define NAMESPACE_END
111 
112 #else
113 
114 NAMESPACE_BEGIN(CryptoPP)
115 
116 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
117 
118 #define CRYPTOPP_CPUID_AVAILABLE
119 
120 // Hide from Doxygen
121 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
122 // These should not be used directly
123 extern CRYPTOPP_DLL bool g_x86DetectionDone;
124 extern CRYPTOPP_DLL bool g_hasMMX;
125 extern CRYPTOPP_DLL bool g_hasISSE;
126 extern CRYPTOPP_DLL bool g_hasSSE2;
127 extern CRYPTOPP_DLL bool g_hasSSSE3;
128 extern CRYPTOPP_DLL bool g_hasSSE4;
129 extern CRYPTOPP_DLL bool g_hasAESNI;
130 extern CRYPTOPP_DLL bool g_hasCLMUL;
131 extern CRYPTOPP_DLL bool g_hasSHA;
132 extern CRYPTOPP_DLL bool g_isP4;
133 extern CRYPTOPP_DLL bool g_hasRDRAND;
134 extern CRYPTOPP_DLL bool g_hasRDSEED;
135 extern CRYPTOPP_DLL bool g_hasPadlockRNG;
136 extern CRYPTOPP_DLL bool g_hasPadlockACE;
137 extern CRYPTOPP_DLL bool g_hasPadlockACE2;
138 extern CRYPTOPP_DLL bool g_hasPadlockPHE;
139 extern CRYPTOPP_DLL bool g_hasPadlockPMM;
140 extern CRYPTOPP_DLL word32 g_cacheLineSize;
141 
142 CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
143 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 input, word32 output[4]);
144 #endif // CRYPTOPP_DOXYGEN_PROCESSING
145 
146 //! \brief Determines MMX availability
147 //! \returns true if MMX is determined to be available, false otherwise
148 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
149 //! the function always returns true for the platform.
150 inline bool HasMMX()
151 {
152 #if CRYPTOPP_BOOL_X64
153  return true;
154 #else
155  if (!g_x86DetectionDone)
156  DetectX86Features();
157  return g_hasMMX;
158 #endif
159 }
160 
161 //! \brief Determines SSE availability
162 //! \returns true if SSE is determined to be available, false otherwise
163 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
164 //! the function always returns true for the platform.
165 inline bool HasISSE()
166 {
167 #if CRYPTOPP_BOOL_X64
168  return true;
169 #else
170  if (!g_x86DetectionDone)
171  DetectX86Features();
172  return g_hasISSE;
173 #endif
174 }
175 
176 //! \brief Determines SSE2 availability
177 //! \returns true if SSE2 is determined to be available, false otherwise
178 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
179 //! the function always returns true for the platform.
180 inline bool HasSSE2()
181 {
182 #if CRYPTOPP_BOOL_X64
183  return true;
184 #else
185  if (!g_x86DetectionDone)
186  DetectX86Features();
187  return g_hasSSE2;
188 #endif
189 }
190 
191 //! \brief Determines SSSE3 availability
192 //! \returns true if SSSE3 is determined to be available, false otherwise
193 //! \details HasSSSE3() is a runtime check performed using CPUID
194 //! \note Some Clang compilers incorrectly omit SSSE3 even though its native to the processor.
195 inline bool HasSSSE3()
196 {
197  if (!g_x86DetectionDone)
198  DetectX86Features();
199  return g_hasSSSE3;
200 }
201 
202 //! \brief Determines SSE4 availability
203 //! \returns true if SSE4.1 and SSE4.2 are determined to be available, false otherwise
204 //! \details HasSSE4() is a runtime check performed using CPUID which requires both SSE4.1 and SSE4.2
205 inline bool HasSSE4()
206 {
207  if (!g_x86DetectionDone)
208  DetectX86Features();
209  return g_hasSSE4;
210 }
211 
212 //! \brief Determines AES-NI availability
213 //! \returns true if AES-NI is determined to be available, false otherwise
214 //! \details HasAESNI() is a runtime check performed using CPUID
215 inline bool HasAESNI()
216 {
217  if (!g_x86DetectionDone)
218  DetectX86Features();
219  return g_hasAESNI;
220 }
221 
222 //! \brief Determines Carryless Multiply availability
223 //! \returns true if pclmulqdq is determined to be available, false otherwise
224 //! \details HasCLMUL() is a runtime check performed using CPUID
225 inline bool HasCLMUL()
226 {
227  if (!g_x86DetectionDone)
228  DetectX86Features();
229  return g_hasCLMUL;
230 }
231 
232 //! \brief Determines SHA availability
233 //! \returns true if SHA is determined to be available, false otherwise
234 //! \details HasSHA() is a runtime check performed using CPUID
235 inline bool HasSHA()
236 {
237  if (!g_x86DetectionDone)
238  DetectX86Features();
239  return g_hasSHA;
240 }
241 
242 //! \brief Determines if the CPU is an Intel P4
243 //! \returns true if the CPU is a P4, false otherwise
244 //! \details IsP4() is a runtime check performed using CPUID
245 inline bool IsP4()
246 {
247  if (!g_x86DetectionDone)
248  DetectX86Features();
249  return g_isP4;
250 }
251 
252 //! \brief Determines RDRAND availability
253 //! \returns true if RDRAND is determined to be available, false otherwise
254 //! \details HasRDRAND() is a runtime check performed using CPUID
255 inline bool HasRDRAND()
256 {
257  if (!g_x86DetectionDone)
258  DetectX86Features();
259  return g_hasRDRAND;
260 }
261 
262 //! \brief Determines RDSEED availability
263 //! \returns true if RDSEED is determined to be available, false otherwise
264 //! \details HasRDSEED() is a runtime check performed using CPUID
265 inline bool HasRDSEED()
266 {
267  if (!g_x86DetectionDone)
268  DetectX86Features();
269  return g_hasRDSEED;
270 }
271 
272 //! \brief Determines Padlock RNG availability
273 //! \returns true if VIA Padlock RNG is determined to be available, false otherwise
274 //! \details HasPadlockRNG() is a runtime check performed using CPUID
275 inline bool HasPadlockRNG()
276 {
277  if (!g_x86DetectionDone)
278  DetectX86Features();
279  return g_hasPadlockRNG;
280 }
281 
282 //! \brief Determines Padlock ACE availability
283 //! \returns true if VIA Padlock ACE is determined to be available, false otherwise
284 //! \details HasPadlockACE() is a runtime check performed using CPUID
285 inline bool HasPadlockACE()
286 {
287  if (!g_x86DetectionDone)
288  DetectX86Features();
289  return g_hasPadlockACE;
290 }
291 
292 //! \brief Determines Padlock ACE2 availability
293 //! \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
294 //! \details HasPadlockACE2() is a runtime check performed using CPUID
295 inline bool HasPadlockACE2()
296 {
297  if (!g_x86DetectionDone)
298  DetectX86Features();
299  return g_hasPadlockACE2;
300 }
301 
302 //! \brief Determines Padlock PHE availability
303 //! \returns true if VIA Padlock PHE is determined to be available, false otherwise
304 //! \details HasPadlockPHE() is a runtime check performed using CPUID
305 inline bool HasPadlockPHE()
306 {
307  if (!g_x86DetectionDone)
308  DetectX86Features();
309  return g_hasPadlockPHE;
310 }
311 
312 //! \brief Determines Padlock PMM availability
313 //! \returns true if VIA Padlock PMM is determined to be available, false otherwise
314 //! \details HasPadlockPMM() is a runtime check performed using CPUID
315 inline bool HasPadlockPMM()
316 {
317  if (!g_x86DetectionDone)
318  DetectX86Features();
319  return g_hasPadlockPMM;
320 }
321 
322 //! \brief Provides the cache line size
323 //! \returns lower bound on the size of a cache line in bytes, if available
324 //! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
325 //! is available. If the value is not available at runtime, then 32 is returned for a 32-bit
326 //! processor and 64 is returned for a 64-bit processor.
327 //! \details x86/x32/x64 uses CPUID to determine the value and its usually accurate. The ARM
328 //! processor equivalent is a privileged instruction, so a compile time value is returned.
329 inline int GetCacheLineSize()
330 {
331  if (!g_x86DetectionDone)
332  DetectX86Features();
333  return g_cacheLineSize;
334 }
335 
336 #elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
337 
338 extern bool g_ArmDetectionDone;
339 extern bool g_hasNEON, g_hasPMULL, g_hasCRC32, g_hasAES, g_hasSHA1, g_hasSHA2;
340 void CRYPTOPP_API DetectArmFeatures();
341 
342 //! \brief Determine if an ARM processor has Advanced SIMD available
343 //! \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
344 //! \details Advanced SIMD instructions are available under Aarch64 (ARM-64) and Aarch32 (ARM-32).
345 //! \details Runtime support requires compile time support. When compiling with GCC, you may
346 //! need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>
347 //! (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.
348 inline bool HasNEON()
349 {
350  if (!g_ArmDetectionDone)
351  DetectArmFeatures();
352  return g_hasNEON;
353 }
354 
355 //! \brief Determine if an ARM processor provides Polynomial Multiplication (long)
356 //! \returns true if the hardware is capable of polynomial multiplications at runtime, false otherwise.
357 //! \details The multiplication instructions are available under Aarch64 (ARM-64) and Aarch32 (ARM-32).
358 //! \details Runtime support requires compile time support. When compiling with GCC, you may
359 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
360 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
361 inline bool HasPMULL()
362 {
363  if (!g_ArmDetectionDone)
364  DetectArmFeatures();
365  return g_hasPMULL;
366 }
367 
368 //! \brief Determine if an ARM processor has CRC32 available
369 //! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
370 //! \details CRC32 instructions provide access to the processor's CRC32 and CRC32-C instructions.
371 //! They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and available under Aarch64
372 //! (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an AArch32 execution environment).
373 //! \details Runtime support requires compile time support. When compiling with GCC, you may
374 //! need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires
375 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.
376 inline bool HasCRC32()
377 {
378  if (!g_ArmDetectionDone)
379  DetectArmFeatures();
380  return g_hasCRC32;
381 }
382 
383 //! \brief Determine if an ARM processor has AES available
384 //! \returns true if the hardware is capable of AES at runtime, false otherwise.
385 //! \details AES is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
386 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
387 //! AArch32 execution environment).
388 //! \details Runtime support requires compile time support. When compiling with GCC, you may
389 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
390 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
391 inline bool HasAES()
392 {
393  if (!g_ArmDetectionDone)
394  DetectArmFeatures();
395  return g_hasAES;
396 }
397 
398 //! \brief Determine if an ARM processor has SHA1 available
399 //! \returns true if the hardware is capable of SHA1 at runtime, false otherwise.
400 //! \details SHA1 is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
401 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
402 //! AArch32 execution environment).
403 //! \details Runtime support requires compile time support. When compiling with GCC, you may
404 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
405 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
406 inline bool HasSHA1()
407 {
408  if (!g_ArmDetectionDone)
409  DetectArmFeatures();
410  return g_hasSHA1;
411 }
412 
413 //! \brief Determine if an ARM processor has SHA2 available
414 //! \returns true if the hardware is capable of SHA2 at runtime, false otherwise.
415 //! \details SHA2 is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
416 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
417 //! AArch32 execution environment).
418 //! \details Runtime support requires compile time support. When compiling with GCC, you may
419 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
420 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
421 inline bool HasSHA2()
422 {
423  if (!g_ArmDetectionDone)
424  DetectArmFeatures();
425  return g_hasSHA2;
426 }
427 
428 //! \brief Provides the cache line size at runtime
429 //! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
430 //! \details GetCacheLineSize() provides is an estimate using CRYPTOPP_L1_CACHE_LINE_SIZE.
431 //! The runtime instructions to query the processor are privileged.
432 inline int GetCacheLineSize()
433 {
434  return CRYPTOPP_L1_CACHE_LINE_SIZE;
435 }
436 
437 #else
438 
439 inline int GetCacheLineSize()
440 {
441  return CRYPTOPP_L1_CACHE_LINE_SIZE;
442 }
443 
444 #endif // X86/X32/X64 and ARM
445 
446 #endif
447 
448 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
449 
450 #ifdef CRYPTOPP_GENERATE_X64_MASM
451  #define AS1(x) x*newline*
452  #define AS2(x, y) x, y*newline*
453  #define AS3(x, y, z) x, y, z*newline*
454  #define ASS(x, y, a, b, c, d) x, y, a*64+b*16+c*4+d*newline*
455  #define ASL(x) label##x:*newline*
456  #define ASJ(x, y, z) x label##y*newline*
457  #define ASC(x, y) x label##y*newline*
458  #define AS_HEX(y) 0##y##h
459 #elif defined(_MSC_VER) || defined(__BORLANDC__)
460  #define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
461  #define AS1(x) __asm {x}
462  #define AS2(x, y) __asm {x, y}
463  #define AS3(x, y, z) __asm {x, y, z}
464  #define ASS(x, y, a, b, c, d) __asm {x, y, (a)*64+(b)*16+(c)*4+(d)}
465  #define ASL(x) __asm {label##x:}
466  #define ASJ(x, y, z) __asm {x label##y}
467  #define ASC(x, y) __asm {x label##y}
468  #define CRYPTOPP_NAKED __declspec(naked)
469  #define AS_HEX(y) 0x##y
470 #else
471  #define CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
472 
473  // define these in two steps to allow arguments to be expanded
474  #define GNU_AS1(x) #x ";" NEW_LINE
475  #define GNU_AS2(x, y) #x ", " #y ";" NEW_LINE
476  #define GNU_AS3(x, y, z) #x ", " #y ", " #z ";" NEW_LINE
477  #define GNU_ASL(x) "\n" #x ":" NEW_LINE
478  #define GNU_ASJ(x, y, z) #x " " #y #z ";" NEW_LINE
479  #define AS1(x) GNU_AS1(x)
480  #define AS2(x, y) GNU_AS2(x, y)
481  #define AS3(x, y, z) GNU_AS3(x, y, z)
482  #define ASS(x, y, a, b, c, d) #x ", " #y ", " #a "*64+" #b "*16+" #c "*4+" #d ";"
483  #define ASL(x) GNU_ASL(x)
484  #define ASJ(x, y, z) GNU_ASJ(x, y, z)
485  #define ASC(x, y) #x " " #y ";"
486  #define CRYPTOPP_NAKED
487  #define AS_HEX(y) 0x##y
488 #endif
489 
490 #define IF0(y)
491 #define IF1(y) y
492 
493 #ifdef CRYPTOPP_GENERATE_X64_MASM
494 #define ASM_MOD(x, y) ((x) MOD (y))
495 #define XMMWORD_PTR XMMWORD PTR
496 #else
497 // GNU assembler doesn't seem to have mod operator
498 #define ASM_MOD(x, y) ((x)-((x)/(y))*(y))
499 // GAS 2.15 doesn't support XMMWORD PTR. it seems necessary only for MASM
500 #define XMMWORD_PTR
501 #endif
502 
503 #if CRYPTOPP_BOOL_X86
504  #define AS_REG_1 ecx
505  #define AS_REG_2 edx
506  #define AS_REG_3 esi
507  #define AS_REG_4 edi
508  #define AS_REG_5 eax
509  #define AS_REG_6 ebx
510  #define AS_REG_7 ebp
511  #define AS_REG_1d ecx
512  #define AS_REG_2d edx
513  #define AS_REG_3d esi
514  #define AS_REG_4d edi
515  #define AS_REG_5d eax
516  #define AS_REG_6d ebx
517  #define AS_REG_7d ebp
518  #define WORD_SZ 4
519  #define WORD_REG(x) e##x
520  #define WORD_PTR DWORD PTR
521  #define AS_PUSH_IF86(x) AS1(push e##x)
522  #define AS_POP_IF86(x) AS1(pop e##x)
523  #define AS_JCXZ jecxz
524 #elif CRYPTOPP_BOOL_X32
525  #define AS_REG_1 ecx
526  #define AS_REG_2 edx
527  #define AS_REG_3 r8d
528  #define AS_REG_4 r9d
529  #define AS_REG_5 eax
530  #define AS_REG_6 r10d
531  #define AS_REG_7 r11d
532  #define AS_REG_1d ecx
533  #define AS_REG_2d edx
534  #define AS_REG_3d r8d
535  #define AS_REG_4d r9d
536  #define AS_REG_5d eax
537  #define AS_REG_6d r10d
538  #define AS_REG_7d r11d
539  #define WORD_SZ 4
540  #define WORD_REG(x) e##x
541  #define WORD_PTR DWORD PTR
542  #define AS_PUSH_IF86(x) AS1(push r##x)
543  #define AS_POP_IF86(x) AS1(pop r##x)
544  #define AS_JCXZ jecxz
545 #elif CRYPTOPP_BOOL_X64
546  #ifdef CRYPTOPP_GENERATE_X64_MASM
547  #define AS_REG_1 rcx
548  #define AS_REG_2 rdx
549  #define AS_REG_3 r8
550  #define AS_REG_4 r9
551  #define AS_REG_5 rax
552  #define AS_REG_6 r10
553  #define AS_REG_7 r11
554  #define AS_REG_1d ecx
555  #define AS_REG_2d edx
556  #define AS_REG_3d r8d
557  #define AS_REG_4d r9d
558  #define AS_REG_5d eax
559  #define AS_REG_6d r10d
560  #define AS_REG_7d r11d
561  #else
562  #define AS_REG_1 rdi
563  #define AS_REG_2 rsi
564  #define AS_REG_3 rdx
565  #define AS_REG_4 rcx
566  #define AS_REG_5 r8
567  #define AS_REG_6 r9
568  #define AS_REG_7 r10
569  #define AS_REG_1d edi
570  #define AS_REG_2d esi
571  #define AS_REG_3d edx
572  #define AS_REG_4d ecx
573  #define AS_REG_5d r8d
574  #define AS_REG_6d r9d
575  #define AS_REG_7d r10d
576  #endif
577  #define WORD_SZ 8
578  #define WORD_REG(x) r##x
579  #define WORD_PTR QWORD PTR
580  #define AS_PUSH_IF86(x)
581  #define AS_POP_IF86(x)
582  #define AS_JCXZ jrcxz
583 #endif
584 
585 // helper macro for stream cipher output
586 #define AS_XMM_OUTPUT4(labelPrefix, inputPtr, outputPtr, x0, x1, x2, x3, t, p0, p1, p2, p3, increment)\
587  AS2( test inputPtr, inputPtr)\
588  ASC( jz, labelPrefix##3)\
589  AS2( test inputPtr, 15)\
590  ASC( jnz, labelPrefix##7)\
591  AS2( pxor xmm##x0, [inputPtr+p0*16])\
592  AS2( pxor xmm##x1, [inputPtr+p1*16])\
593  AS2( pxor xmm##x2, [inputPtr+p2*16])\
594  AS2( pxor xmm##x3, [inputPtr+p3*16])\
595  AS2( add inputPtr, increment*16)\
596  ASC( jmp, labelPrefix##3)\
597  ASL(labelPrefix##7)\
598  AS2( movdqu xmm##t, [inputPtr+p0*16])\
599  AS2( pxor xmm##x0, xmm##t)\
600  AS2( movdqu xmm##t, [inputPtr+p1*16])\
601  AS2( pxor xmm##x1, xmm##t)\
602  AS2( movdqu xmm##t, [inputPtr+p2*16])\
603  AS2( pxor xmm##x2, xmm##t)\
604  AS2( movdqu xmm##t, [inputPtr+p3*16])\
605  AS2( pxor xmm##x3, xmm##t)\
606  AS2( add inputPtr, increment*16)\
607  ASL(labelPrefix##3)\
608  AS2( test outputPtr, 15)\
609  ASC( jnz, labelPrefix##8)\
610  AS2( movdqa [outputPtr+p0*16], xmm##x0)\
611  AS2( movdqa [outputPtr+p1*16], xmm##x1)\
612  AS2( movdqa [outputPtr+p2*16], xmm##x2)\
613  AS2( movdqa [outputPtr+p3*16], xmm##x3)\
614  ASC( jmp, labelPrefix##9)\
615  ASL(labelPrefix##8)\
616  AS2( movdqu [outputPtr+p0*16], xmm##x0)\
617  AS2( movdqu [outputPtr+p1*16], xmm##x1)\
618  AS2( movdqu [outputPtr+p2*16], xmm##x2)\
619  AS2( movdqu [outputPtr+p3*16], xmm##x3)\
620  ASL(labelPrefix##9)\
621  AS2( add outputPtr, increment*16)
622 
623 #endif // X86/X32/X64
624 
625 NAMESPACE_END
626 
627 // Issue 340
628 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
629 # pragma GCC diagnostic pop
630 #endif
631 
632 #endif // CRYPTOPP_CPU_H
bool HasSHA()
Determines SHA availability.
Definition: cpu.h:235
bool HasISSE()
Determines SSE availability.
Definition: cpu.h:165
bool HasSSE4()
Determines SSE4 availability.
Definition: cpu.h:205
bool HasSSSE3()
Determines SSSE3 availability.
Definition: cpu.h:195
bool HasPadlockRNG()
Determines Padlock RNG availability.
Definition: cpu.h:275
bool IsP4()
Determines if the CPU is an Intel P4.
Definition: cpu.h:245
Library configuration file.
int GetCacheLineSize()
Provides the cache line size.
Definition: cpu.h:329
bool HasRDRAND()
Determines RDRAND availability.
Definition: cpu.h:255
bool HasRDSEED()
Determines RDSEED availability.
Definition: cpu.h:265
bool HasCLMUL()
Determines Carryless Multiply availability.
Definition: cpu.h:225
bool HasPadlockACE2()
Determines Padlock ACE2 availability.
Definition: cpu.h:295
bool HasPadlockPHE()
Determines Padlock PHE availability.
Definition: cpu.h:305
bool HasPadlockPMM()
Determines Padlock PMM availability.
Definition: cpu.h:315
bool HasAESNI()
Determines AES-NI availability.
Definition: cpu.h:215
bool HasSSE2()
Determines SSE2 availability.
Definition: cpu.h:180
bool HasMMX()
Determines MMX availability.
Definition: cpu.h:150
Crypto++ library namespace.
bool HasPadlockACE()
Determines Padlock ACE availability.
Definition: cpu.h:285