Crypto++  8.2
Free C++ class library of cryptographic schemes
cpu.h
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1 // cpu.h - originally written and placed in the public domain by Wei Dai
2 // updated for ARM and PowerPC by Jeffrey Walton.
3 // updated to split CPU_Query() and CPU_Probe() by Jeffrey Walton.
4 
5 /// \file cpu.h
6 /// \brief Functions for CPU features and intrinsics
7 /// \details The CPU functions are used in IA-32, ARM and PowerPC code paths. The
8 /// functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.
9 /// \details Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms
10 /// a two-part strategy is used. First, the library attempts to *Query* the OS for a feature,
11 /// like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe*
12 /// the cpu executing an instruction and an observe a SIGILL if unsupported. The general
13 /// pattern used by the library is:
14 /// <pre>
15 /// g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();
16 /// g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();
17 /// g_hasAES = CPU_QueryAES() || CPU_ProbeAES();
18 /// </pre>
19 /// \details Generally speaking, CPU_Query() is in the source file <tt>cpu.cpp</tt> because it
20 /// does not require special architectural flags. CPU_Probe() is in a source file that recieves
21 /// architectural flags, like <tt>sse_simd.cpp</tt>, <tt>neon_simd.cpp</tt> and
22 /// <tt>ppc_simd.cpp</tt>. For example, compiling <tt>neon_simd.cpp</tt> on an ARM64 machine will
23 /// have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture
24 /// (ISA) available.
25 /// \details The cpu probes are expensive when compared to a standard OS feature query. The library
26 /// also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to
27 /// corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL
28 /// experienced the same problem and moved away from SIGILL probes on Apple.
29 
30 #ifndef CRYPTOPP_CPU_H
31 #define CRYPTOPP_CPU_H
32 
33 #include "config.h"
34 
35 // Issue 340
36 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
37 # pragma GCC diagnostic push
38 # pragma GCC diagnostic ignored "-Wconversion"
39 # pragma GCC diagnostic ignored "-Wsign-conversion"
40 #endif
41 
42 // Applies to both X86/X32/X64 and ARM32/ARM64
43 #if defined(CRYPTOPP_LLVM_CLANG_VERSION) || defined(CRYPTOPP_APPLE_CLANG_VERSION)
44  #define NEW_LINE "\n"
45  #define INTEL_PREFIX ".intel_syntax;"
46  #define INTEL_NOPREFIX ".intel_syntax;"
47  #define ATT_PREFIX ".att_syntax;"
48  #define ATT_NOPREFIX ".att_syntax;"
49 #elif defined(__GNUC__)
50  #define NEW_LINE
51  #define INTEL_PREFIX ".intel_syntax prefix;"
52  #define INTEL_NOPREFIX ".intel_syntax noprefix;"
53  #define ATT_PREFIX ".att_syntax prefix;"
54  #define ATT_NOPREFIX ".att_syntax noprefix;"
55 #else
56  #define NEW_LINE
57  #define INTEL_PREFIX
58  #define INTEL_NOPREFIX
59  #define ATT_PREFIX
60  #define ATT_NOPREFIX
61 #endif
62 
63 #ifdef CRYPTOPP_GENERATE_X64_MASM
64 
65 #define CRYPTOPP_X86_ASM_AVAILABLE
66 #define CRYPTOPP_BOOL_X64 1
67 #define CRYPTOPP_SSE2_ASM_AVAILABLE 1
68 #define NAMESPACE_END
69 
70 #else
71 
72 NAMESPACE_BEGIN(CryptoPP)
73 
74 // ***************************** IA-32 ***************************** //
75 
76 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
77 
78 #define CRYPTOPP_CPUID_AVAILABLE 1
79 
80 // Hide from Doxygen
81 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
82 // These should not be used directly
83 extern CRYPTOPP_DLL bool g_x86DetectionDone;
84 extern CRYPTOPP_DLL bool g_hasSSE2;
85 extern CRYPTOPP_DLL bool g_hasSSSE3;
86 extern CRYPTOPP_DLL bool g_hasSSE41;
87 extern CRYPTOPP_DLL bool g_hasSSE42;
88 extern CRYPTOPP_DLL bool g_hasMOVBE;
89 extern CRYPTOPP_DLL bool g_hasAESNI;
90 extern CRYPTOPP_DLL bool g_hasCLMUL;
91 extern CRYPTOPP_DLL bool g_hasAVX;
92 extern CRYPTOPP_DLL bool g_hasAVX2;
93 extern CRYPTOPP_DLL bool g_hasSHA;
94 extern CRYPTOPP_DLL bool g_hasADX;
95 extern CRYPTOPP_DLL bool g_isP4;
96 extern CRYPTOPP_DLL bool g_hasRDRAND;
97 extern CRYPTOPP_DLL bool g_hasRDSEED;
98 extern CRYPTOPP_DLL bool g_hasPadlockRNG;
99 extern CRYPTOPP_DLL bool g_hasPadlockACE;
100 extern CRYPTOPP_DLL bool g_hasPadlockACE2;
101 extern CRYPTOPP_DLL bool g_hasPadlockPHE;
102 extern CRYPTOPP_DLL bool g_hasPadlockPMM;
103 extern CRYPTOPP_DLL word32 g_cacheLineSize;
104 
105 CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
106 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[4]);
107 #endif // CRYPTOPP_DOXYGEN_PROCESSING
108 
109 /// \name IA-32 CPU FEATURES
110 //@{
111 
112 /// \brief Determine SSE2 availability
113 /// \returns true if SSE2 is determined to be available, false otherwise
114 /// \details MMX, SSE and SSE2 are core processor features for x86_64, and
115 /// the function return value is based on OSXSAVE. On i386 both
116 /// SSE2 and OSXSAVE are used for the return value.
117 /// \note This function is only available on Intel IA-32 platforms
118 inline bool HasSSE2()
119 {
120 #if (CRYPTOPP_SSE2_ASM_AVAILABLE || CRYPTOPP_SSE2_INTRIN_AVAILABLE)
121  if (!g_x86DetectionDone)
122  DetectX86Features();
123  return g_hasSSE2;
124 #else
125  return false;
126 #endif
127 }
128 
129 /// \brief Determine SSSE3 availability
130 /// \returns true if SSSE3 is determined to be available, false otherwise
131 /// \details HasSSSE3() is a runtime check performed using CPUID
132 /// \note This function is only available on Intel IA-32 platforms
133 inline bool HasSSSE3()
134 {
135 #if CRYPTOPP_SSSE3_AVAILABLE
136  if (!g_x86DetectionDone)
137  DetectX86Features();
138  return g_hasSSSE3;
139 #else
140  return false;
141 #endif
142 }
143 
144 /// \brief Determine SSE4.1 availability
145 /// \returns true if SSE4.1 is determined to be available, false otherwise
146 /// \details HasSSE41() is a runtime check performed using CPUID
147 /// \note This function is only available on Intel IA-32 platforms
148 inline bool HasSSE41()
149 {
150 #if CRYPTOPP_SSE41_AVAILABLE
151  if (!g_x86DetectionDone)
152  DetectX86Features();
153  return g_hasSSE41;
154 #else
155  return false;
156 #endif
157 }
158 
159 /// \brief Determine SSE4.2 availability
160 /// \returns true if SSE4.2 is determined to be available, false otherwise
161 /// \details HasSSE42() is a runtime check performed using CPUID
162 /// \note This function is only available on Intel IA-32 platforms
163 inline bool HasSSE42()
164 {
165 #if CRYPTOPP_SSE42_AVAILABLE
166  if (!g_x86DetectionDone)
167  DetectX86Features();
168  return g_hasSSE42;
169 #else
170  return false;
171 #endif
172 }
173 
174 /// \brief Determine MOVBE availability
175 /// \returns true if MOVBE is determined to be available, false otherwise
176 /// \details HasMOVBE() is a runtime check performed using CPUID
177 /// \since Crypto++ 8.3
178 /// \note This function is only available on Intel IA-32 platforms
179 inline bool HasMOVBE()
180 {
181 #if CRYPTOPP_SSE42_AVAILABLE
182  if (!g_x86DetectionDone)
183  DetectX86Features();
184  return g_hasMOVBE;
185 #else
186  return false;
187 #endif
188 }
189 
190 /// \brief Determine AES-NI availability
191 /// \returns true if AES-NI is determined to be available, false otherwise
192 /// \details HasAESNI() is a runtime check performed using CPUID
193 /// \since Crypto++ 5.6.1
194 /// \note This function is only available on Intel IA-32 platforms
195 inline bool HasAESNI()
196 {
197 #if CRYPTOPP_AESNI_AVAILABLE
198  if (!g_x86DetectionDone)
199  DetectX86Features();
200  return g_hasAESNI;
201 #else
202  return false;
203 #endif
204 }
205 
206 /// \brief Determine Carryless Multiply availability
207 /// \returns true if pclmulqdq is determined to be available, false otherwise
208 /// \details HasCLMUL() is a runtime check performed using CPUID
209 /// \since Crypto++ 5.6.1
210 /// \note This function is only available on Intel IA-32 platforms
211 inline bool HasCLMUL()
212 {
213 #if CRYPTOPP_CLMUL_AVAILABLE
214  if (!g_x86DetectionDone)
215  DetectX86Features();
216  return g_hasCLMUL;
217 #else
218  return false;
219 #endif
220 }
221 
222 /// \brief Determine SHA availability
223 /// \returns true if SHA is determined to be available, false otherwise
224 /// \details HasSHA() is a runtime check performed using CPUID
225 /// \since Crypto++ 6.0
226 /// \note This function is only available on Intel IA-32 platforms
227 inline bool HasSHA()
228 {
229 #if CRYPTOPP_SHANI_AVAILABLE
230  if (!g_x86DetectionDone)
231  DetectX86Features();
232  return g_hasSHA;
233 #else
234  return false;
235 #endif
236 }
237 
238 /// \brief Determine ADX availability
239 /// \returns true if ADX is determined to be available, false otherwise
240 /// \details HasADX() is a runtime check performed using CPUID
241 /// \since Crypto++ 7.0
242 /// \note This function is only available on Intel IA-32 platforms
243 inline bool HasADX()
244 {
245 #if CRYPTOPP_ADX_AVAILABLE
246  if (!g_x86DetectionDone)
247  DetectX86Features();
248  return g_hasADX;
249 #else
250  return false;
251 #endif
252 }
253 
254 /// \brief Determine AVX availability
255 /// \returns true if AVX is determined to be available, false otherwise
256 /// \details HasAVX() is a runtime check performed using CPUID
257 /// \since Crypto++ 8.0
258 /// \note This function is only available on Intel IA-32 platforms
259 inline bool HasAVX()
260 {
261 #if CRYPTOPP_AVX_AVAILABLE
262  if (!g_x86DetectionDone)
263  DetectX86Features();
264  return g_hasAVX;
265 #else
266  return false;
267 #endif
268 }
269 
270 /// \brief Determine AVX2 availability
271 /// \returns true if AVX2 is determined to be available, false otherwise
272 /// \details HasAVX2() is a runtime check performed using CPUID
273 /// \since Crypto++ 8.0
274 /// \note This function is only available on Intel IA-32 platforms
275 inline bool HasAVX2()
276 {
277 #if CRYPTOPP_AVX2_AVAILABLE
278  if (!g_x86DetectionDone)
279  DetectX86Features();
280  return g_hasAVX2;
281 #else
282  return false;
283 #endif
284 }
285 
286 /// \brief Determine RDRAND availability
287 /// \returns true if RDRAND is determined to be available, false otherwise
288 /// \details HasRDRAND() is a runtime check performed using CPUID
289 /// \note This function is only available on Intel IA-32 platforms
290 inline bool HasRDRAND()
291 {
292 #if CRYPTOPP_RDRAND_AVAILABLE
293  if (!g_x86DetectionDone)
294  DetectX86Features();
295  return g_hasRDRAND;
296 #else
297  return false;
298 #endif
299 }
300 
301 /// \brief Determine RDSEED availability
302 /// \returns true if RDSEED is determined to be available, false otherwise
303 /// \details HasRDSEED() is a runtime check performed using CPUID
304 /// \note This function is only available on Intel IA-32 platforms
305 inline bool HasRDSEED()
306 {
307 #if CRYPTOPP_RDSEED_AVAILABLE
308  if (!g_x86DetectionDone)
309  DetectX86Features();
310  return g_hasRDSEED;
311 #else
312  return false;
313 #endif
314 }
315 
316 /// \brief Determine Padlock RNG availability
317 /// \returns true if VIA Padlock RNG is determined to be available, false otherwise
318 /// \details HasPadlockRNG() is a runtime check performed using CPUID
319 /// \note This function is only available on Intel IA-32 platforms
320 inline bool HasPadlockRNG()
321 {
322 #if CRYPTOPP_PADLOCK_RNG_AVAILABLE
323  if (!g_x86DetectionDone)
324  DetectX86Features();
325  return g_hasPadlockRNG;
326 #else
327  return false;
328 #endif
329 }
330 
331 /// \brief Determine Padlock ACE availability
332 /// \returns true if VIA Padlock ACE is determined to be available, false otherwise
333 /// \details HasPadlockACE() is a runtime check performed using CPUID
334 /// \note This function is only available on Intel IA-32 platforms
335 inline bool HasPadlockACE()
336 {
337 #if CRYPTOPP_PADLOCK_ACE_AVAILABLE
338  if (!g_x86DetectionDone)
339  DetectX86Features();
340  return g_hasPadlockACE;
341 #else
342  return false;
343 #endif
344 }
345 
346 /// \brief Determine Padlock ACE2 availability
347 /// \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
348 /// \details HasPadlockACE2() is a runtime check performed using CPUID
349 /// \note This function is only available on Intel IA-32 platforms
350 inline bool HasPadlockACE2()
351 {
352 #if CRYPTOPP_PADLOCK_ACE2_AVAILABLE
353  if (!g_x86DetectionDone)
354  DetectX86Features();
355  return g_hasPadlockACE2;
356 #else
357  return false;
358 #endif
359 }
360 
361 /// \brief Determine Padlock PHE availability
362 /// \returns true if VIA Padlock PHE is determined to be available, false otherwise
363 /// \details HasPadlockPHE() is a runtime check performed using CPUID
364 /// \note This function is only available on Intel IA-32 platforms
365 inline bool HasPadlockPHE()
366 {
367 #if CRYPTOPP_PADLOCK_PHE_AVAILABLE
368  if (!g_x86DetectionDone)
369  DetectX86Features();
370  return g_hasPadlockPHE;
371 #else
372  return false;
373 #endif
374 }
375 
376 /// \brief Determine Padlock PMM availability
377 /// \returns true if VIA Padlock PMM is determined to be available, false otherwise
378 /// \details HasPadlockPMM() is a runtime check performed using CPUID
379 /// \note This function is only available on Intel IA-32 platforms
380 inline bool HasPadlockPMM()
381 {
382 #if CRYPTOPP_PADLOCK_PMM_AVAILABLE
383  if (!g_x86DetectionDone)
384  DetectX86Features();
385  return g_hasPadlockPMM;
386 #else
387  return false;
388 #endif
389 }
390 
391 /// \brief Determine if the CPU is an Intel P4
392 /// \returns true if the CPU is a P4, false otherwise
393 /// \details IsP4() is a runtime check performed using CPUID
394 /// \note This function is only available on Intel IA-32 platforms
395 inline bool IsP4()
396 {
397  if (!g_x86DetectionDone)
398  DetectX86Features();
399  return g_isP4;
400 }
401 
402 /// \brief Provides the cache line size
403 /// \returns lower bound on the size of a cache line in bytes, if available
404 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
405 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit
406 /// processor and 64 is returned for a 64-bit processor.
407 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
408 /// and AIX also makes the value available to user space and it is also usually accurate. The
409 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned.
410 inline int GetCacheLineSize()
411 {
412  if (!g_x86DetectionDone)
413  DetectX86Features();
414  return g_cacheLineSize;
415 }
416 //@}
417 
418 #endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
419 
420 // ***************************** ARM-32, Aarch32 and Aarch64 ***************************** //
421 
422 #if CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8 || CRYPTOPP_DOXYGEN_PROCESSING
423 
424 // Hide from Doxygen
425 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
426 extern bool g_ArmDetectionDone;
427 extern bool g_hasARMv7;
428 extern bool g_hasNEON;
429 extern bool g_hasPMULL;
430 extern bool g_hasCRC32;
431 extern bool g_hasAES;
432 extern bool g_hasSHA1;
433 extern bool g_hasSHA2;
434 extern bool g_hasSHA512;
435 extern bool g_hasSHA3;
436 extern bool g_hasSM3;
437 extern bool g_hasSM4;
438 void CRYPTOPP_API DetectArmFeatures();
439 #endif // CRYPTOPP_DOXYGEN_PROCESSING
440 
441 /// \name ARM A-32, Aarch32 and AArch64 CPU FEATURES
442 //@{
443 
444 /// \brief Determine if an ARM processor is ARMv7 or above
445 /// \returns true if the hardware is ARMv7 or above, false otherwise.
446 /// \details Some AES code requires ARMv7 or above
447 /// \since Crypto++ 8.0
448 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
449 inline bool HasARMv7()
450 {
451  // ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64
452 #if defined(__aarch32__) || defined(__aarch64__)
453  return true;
454 #else
455  if (!g_ArmDetectionDone)
456  DetectArmFeatures();
457  return g_hasARMv7;
458 #endif
459 }
460 
461 /// \brief Determine if an ARM processor has Advanced SIMD available
462 /// \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
463 /// \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.
464 /// \details Runtime support requires compile time support. When compiling with GCC, you may
465 /// need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>
466 /// (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.
467 /// \since Crypto++ 5.6.4
468 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
469 inline bool HasNEON()
470 {
471  // ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64
472 #if defined(__aarch32__) || defined(__aarch64__)
473  return true;
474 #else
475  if (!g_ArmDetectionDone)
476  DetectArmFeatures();
477  return g_hasNEON;
478 #endif
479 }
480 
481 /// \brief Determine if an ARM processor provides Polynomial Multiplication
482 /// \returns true if the hardware is capable of polynomial multiplications at runtime,
483 /// false otherwise.
484 /// \details The multiplication instructions are available under Aarch32 and Aarch64.
485 /// \details Runtime support requires compile time support. When compiling with GCC,
486 /// you may need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
487 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
488 /// \since Crypto++ 5.6.4
489 /// \note This function is only available on Aarch32 and Aarch64 platforms
490 inline bool HasPMULL()
491 {
492 #if defined(__aarch32__) || defined(__aarch64__)
493  if (!g_ArmDetectionDone)
494  DetectArmFeatures();
495  return g_hasPMULL;
496 #else
497  return false;
498 #endif
499 }
500 
501 /// \brief Determine if an ARM processor has CRC32 available
502 /// \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
503 /// \details CRC32 instructions provide access to the processor's CRC-32 and CRC-32C
504 /// instructions. They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and
505 /// available under Aarch32 and Aarch64.
506 /// \details Runtime support requires compile time support. When compiling with GCC,
507 /// you may need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires
508 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.
509 /// \since Crypto++ 5.6.4
510 /// \note This function is only available on Aarch32 and Aarch64 platforms
511 inline bool HasCRC32()
512 {
513 #if defined(__aarch32__) || defined(__aarch64__)
514  if (!g_ArmDetectionDone)
515  DetectArmFeatures();
516  return g_hasCRC32;
517 #else
518  return false;
519 #endif
520 }
521 
522 /// \brief Determine if an ARM processor has AES available
523 /// \returns true if the hardware is capable of AES at runtime, false otherwise.
524 /// \details AES is part of the optional Crypto extensions on Aarch32 and Aarch64. They are
525 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
526 /// \details Runtime support requires compile time support. When compiling with GCC, you may
527 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
528 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
529 /// \since Crypto++ 5.6.4
530 /// \note This function is only available on Aarch32 and Aarch64 platforms
531 inline bool HasAES()
532 {
533 #if defined(__aarch32__) || defined(__aarch64__)
534  if (!g_ArmDetectionDone)
535  DetectArmFeatures();
536  return g_hasAES;
537 #else
538  return false;
539 #endif
540 }
541 
542 /// \brief Determine if an ARM processor has SHA1 available
543 /// \returns true if the hardware is capable of SHA1 at runtime, false otherwise.
544 /// \details SHA1 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are
545 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
546 /// \details Runtime support requires compile time support. When compiling with GCC, you may
547 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
548 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
549 /// \since Crypto++ 5.6.4
550 /// \note This function is only available on Aarch32 and Aarch64 platforms
551 inline bool HasSHA1()
552 {
553 #if defined(__aarch32__) || defined(__aarch64__)
554  if (!g_ArmDetectionDone)
555  DetectArmFeatures();
556  return g_hasSHA1;
557 #else
558  return false;
559 #endif
560 }
561 
562 /// \brief Determine if an ARM processor has SHA256 available
563 /// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.
564 /// \details SHA256 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are
565 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
566 /// \details Runtime support requires compile time support. When compiling with GCC, you may
567 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
568 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
569 /// \since Crypto++ 5.6.4
570 /// \note This function is only available on Aarch32 and Aarch64 platforms
571 inline bool HasSHA2()
572 {
573 #if defined(__aarch32__) || defined(__aarch64__)
574  if (!g_ArmDetectionDone)
575  DetectArmFeatures();
576  return g_hasSHA2;
577 #else
578  return false;
579 #endif
580 }
581 
582 /// \brief Determine if an ARM processor has SHA512 available
583 /// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.
584 /// \details SHA512 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
585 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
586 /// \details Runtime support requires compile time support. When compiling with GCC, you
587 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
588 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
589 /// \since Crypto++ 8.0
590 /// \note This function is only available on Aarch32 and Aarch64 platforms
591 inline bool HasSHA512()
592 {
593 #if defined(__aarch32__) || defined(__aarch64__)
594  if (!g_ArmDetectionDone)
595  DetectArmFeatures();
596  return g_hasSHA512;
597 #else
598  return false;
599 #endif
600 }
601 
602 /// \brief Determine if an ARM processor has SHA3 available
603 /// \returns true if the hardware is capable of SHA3 at runtime, false otherwise.
604 /// \details SHA3 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
605 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
606 /// \details Runtime support requires compile time support. When compiling with GCC, you
607 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
608 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
609 /// \since Crypto++ 8.0
610 /// \note This function is only available on Aarch32 and Aarch64 platforms
611 inline bool HasSHA3()
612 {
613 #if defined(__aarch32__) || defined(__aarch64__)
614  if (!g_ArmDetectionDone)
615  DetectArmFeatures();
616  return g_hasSHA3;
617 #else
618  return false;
619 #endif
620 }
621 
622 /// \brief Determine if an ARM processor has SM3 available
623 /// \returns true if the hardware is capable of SM3 at runtime, false otherwise.
624 /// \details SM3 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
625 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
626 /// \details Runtime support requires compile time support. When compiling with GCC, you
627 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
628 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
629 /// \since Crypto++ 8.0
630 /// \note This function is only available on Aarch32 and Aarch64 platforms
631 inline bool HasSM3()
632 {
633 #if defined(__aarch32__) || defined(__aarch64__)
634  if (!g_ArmDetectionDone)
635  DetectArmFeatures();
636  return g_hasSM3;
637 #else
638  return false;
639 #endif
640 }
641 
642 /// \brief Determine if an ARM processor has SM4 available
643 /// \returns true if the hardware is capable of SM4 at runtime, false otherwise.
644 /// \details SM4 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
645 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
646 /// \details Runtime support requires compile time support. When compiling with GCC, you
647 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
648 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
649 /// \since Crypto++ 8.0
650 /// \note This function is only available on Aarch32 and Aarch64 platforms
651 inline bool HasSM4()
652 {
653 #if defined(__aarch32__) || defined(__aarch64__)
654  if (!g_ArmDetectionDone)
655  DetectArmFeatures();
656  return g_hasSM4;
657 #else
658  return false;
659 #endif
660 }
661 
662 //@}
663 
664 #endif // CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8
665 
666 // ***************************** PowerPC ***************************** //
667 
668 #if CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64 || CRYPTOPP_DOXYGEN_PROCESSING
669 
670 // Hide from Doxygen
671 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
672 extern bool g_PowerpcDetectionDone;
673 extern bool g_hasAltivec;
674 extern bool g_hasPower7;
675 extern bool g_hasPower8;
676 extern bool g_hasPower9;
677 extern bool g_hasAES;
678 extern bool g_hasPMULL;
679 extern bool g_hasSHA256;
680 extern bool g_hasSHA512;
681 extern bool g_hasDARN;
682 extern word32 g_cacheLineSize;
683 void CRYPTOPP_API DetectPowerpcFeatures();
684 #endif // CRYPTOPP_DOXYGEN_PROCESSING
685 
686 /// \name POWERPC CPU FEATURES
687 //@{
688 
689 /// \brief Determine if a PowerPC processor has Altivec available
690 /// \returns true if the hardware is capable of Altivec at runtime, false otherwise.
691 /// \details Altivec instructions are available on modern PowerPCs.
692 /// \details Runtime support requires compile time support. When compiling with GCC, you may
693 /// need to compile with <tt>-mcpu=power4</tt>; while IBM XL C/C++ compilers require
694 /// <tt>-qarch=pwr6 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
695 /// \note This function is only available on PowerPC and PowerPC-64 platforms
696 inline bool HasAltivec()
697 {
698 #if CRYPTOPP_ALTIVEC_AVAILABLE
699  if (!g_PowerpcDetectionDone)
700  DetectPowerpcFeatures();
701  return g_hasAltivec;
702 #else
703  return false;
704 #endif
705 }
706 
707 /// \brief Determine if a PowerPC processor has Power7 available
708 /// \returns true if the hardware is capable of Power7 at runtime, false otherwise.
709 /// \details Runtime support requires compile time support. When compiling with GCC, you may
710 /// need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require
711 /// <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
712 /// \note This function is only available on PowerPC and PowerPC-64 platforms
713 inline bool HasPower7()
714 {
715 #if CRYPTOPP_POWER7_AVAILABLE
716  if (!g_PowerpcDetectionDone)
717  DetectPowerpcFeatures();
718  return g_hasPower7;
719 #else
720  return false;
721 #endif
722 }
723 
724 /// \brief Determine if a PowerPC processor has Power8 available
725 /// \returns true if the hardware is capable of Power8 at runtime, false otherwise.
726 /// \details Runtime support requires compile time support. When compiling with GCC, you may
727 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
728 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
729 /// \note This function is only available on PowerPC and PowerPC-64 platforms
730 inline bool HasPower8()
731 {
732 #if CRYPTOPP_POWER8_AVAILABLE
733  if (!g_PowerpcDetectionDone)
734  DetectPowerpcFeatures();
735  return g_hasPower8;
736 #else
737  return false;
738 #endif
739 }
740 
741 /// \brief Determine if a PowerPC processor has Power9 available
742 /// \returns true if the hardware is capable of Power9 at runtime, false otherwise.
743 /// \details Runtime support requires compile time support. When compiling with GCC, you may
744 /// need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require
745 /// <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
746 /// \note This function is only available on PowerPC and PowerPC-64 platforms
747 inline bool HasPower9()
748 {
749 #if CRYPTOPP_POWER9_AVAILABLE
750  if (!g_PowerpcDetectionDone)
751  DetectPowerpcFeatures();
752  return g_hasPower9;
753 #else
754  return false;
755 #endif
756 }
757 
758 /// \brief Determine if a PowerPC processor has AES available
759 /// \returns true if the hardware is capable of AES at runtime, false otherwise.
760 /// \details AES is part of the in-crypto extensions on Power8 and Power9.
761 /// \details Runtime support requires compile time support. When compiling with GCC, you may
762 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
763 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
764 /// \note This function is only available on PowerPC and PowerPC-64 platforms
765 inline bool HasAES()
766 {
767 #if CRYPTOPP_POWER8_AES_AVAILABLE
768  if (!g_PowerpcDetectionDone)
769  DetectPowerpcFeatures();
770  return g_hasAES;
771 #else
772  return false;
773 #endif
774 }
775 
776 /// \brief Determine if a PowerPC processor has Polynomial Multiply available
777 /// \returns true if the hardware is capable of PMULL at runtime, false otherwise.
778 /// \details PMULL is part of the in-crypto extensions on Power8 and Power9.
779 /// \details Runtime support requires compile time support. When compiling with GCC, you may
780 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
781 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
782 /// \note This function is only available on PowerPC and PowerPC-64 platforms
783 inline bool HasPMULL()
784 {
785 #if CRYPTOPP_POWER8_VMULL_AVAILABLE
786  if (!g_PowerpcDetectionDone)
787  DetectPowerpcFeatures();
788  return g_hasPMULL;
789 #else
790  return false;
791 #endif
792 }
793 
794 /// \brief Determine if a PowerPC processor has SHA256 available
795 /// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.
796 /// \details SHA is part of the in-crypto extensions on Power8 and Power9.
797 /// \details Runtime support requires compile time support. When compiling with GCC, you may
798 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
799 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
800 /// \note This function is only available on PowerPC and PowerPC-64 platforms
801 inline bool HasSHA256()
802 {
803 #if CRYPTOPP_POWER8_SHA_AVAILABLE
804  if (!g_PowerpcDetectionDone)
805  DetectPowerpcFeatures();
806  return g_hasSHA256;
807 #else
808  return false;
809 #endif
810 }
811 
812 /// \brief Determine if a PowerPC processor has SHA512 available
813 /// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.
814 /// \details SHA is part of the in-crypto extensions on Power8 and Power9.
815 /// \details Runtime support requires compile time support. When compiling with GCC, you may
816 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
817 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
818 /// \note This function is only available on PowerPC and PowerPC-64 platforms
819 inline bool HasSHA512()
820 {
821 #if CRYPTOPP_POWER8_SHA_AVAILABLE
822  if (!g_PowerpcDetectionDone)
823  DetectPowerpcFeatures();
824  return g_hasSHA512;
825 #else
826  return false;
827 #endif
828 }
829 
830 /// \brief Determine if a PowerPC processor has DARN available
831 /// \returns true if the hardware is capable of DARN at runtime, false otherwise.
832 /// \details Runtime support requires compile time support. When compiling with GCC, you may
833 /// need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require
834 /// <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
835 /// \note This function is only available on PowerPC and PowerPC-64 platforms
836 inline bool HasDARN()
837 {
838 #if CRYPTOPP_POWER9_AVAILABLE
839  if (!g_PowerpcDetectionDone)
840  DetectPowerpcFeatures();
841  // see comments in cpu.cpp
842 # if defined(__ibmxl__) && defined(__linux__)
843  return false;
844 # else
845  return g_hasDARN;
846 # endif
847 #else
848  return false;
849 #endif
850 }
851 
852 /// \brief Provides the cache line size
853 /// \returns lower bound on the size of a cache line in bytes, if available
854 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
855 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit
856 /// processor and 64 is returned for a 64-bit processor.
857 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
858 /// and AIX also makes the value available to user space and it is also usually accurate. The
859 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned.
860 inline int GetCacheLineSize()
861 {
862  if (!g_PowerpcDetectionDone)
863  DetectPowerpcFeatures();
864  return g_cacheLineSize;
865 }
866 
867 //@}
868 
869 #endif // CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64
870 
871 // ***************************** L1 cache line ***************************** //
872 
873 // Non-Intel systems
874 #if !(CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64)
875 /// \brief Provides the cache line size
876 /// \returns lower bound on the size of a cache line in bytes, if available
877 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
878 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit
879 /// processor and 64 is returned for a 64-bit processor.
880 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
881 /// and AIX also makes the value available to user space and it is also usually accurate. The
882 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned.
883 inline int GetCacheLineSize()
884 {
885  return CRYPTOPP_L1_CACHE_LINE_SIZE;
886 }
887 #endif // Non-Intel systems
888 
889 #endif // CRYPTOPP_GENERATE_X64_MASM
890 
891 // ***************************** Inline ASM Helper ***************************** //
892 
893 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
894 
895 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
896 
897 #ifdef CRYPTOPP_GENERATE_X64_MASM
898  #define AS1(x) x*newline*
899  #define AS2(x, y) x, y*newline*
900  #define AS3(x, y, z) x, y, z*newline*
901  #define ASS(x, y, a, b, c, d) x, y, a*64+b*16+c*4+d*newline*
902  #define ASL(x) label##x:*newline*
903  #define ASJ(x, y, z) x label##y*newline*
904  #define ASC(x, y) x label##y*newline*
905  #define AS_HEX(y) 0##y##h
906 #elif defined(_MSC_VER) || defined(__BORLANDC__)
907  #define AS1(x) __asm {x}
908  #define AS2(x, y) __asm {x, y}
909  #define AS3(x, y, z) __asm {x, y, z}
910  #define ASS(x, y, a, b, c, d) __asm {x, y, (a)*64+(b)*16+(c)*4+(d)}
911  #define ASL(x) __asm {label##x:}
912  #define ASJ(x, y, z) __asm {x label##y}
913  #define ASC(x, y) __asm {x label##y}
914  #define CRYPTOPP_NAKED __declspec(naked)
915  #define AS_HEX(y) 0x##y
916 #else
917  // define these in two steps to allow arguments to be expanded
918  #define GNU_AS1(x) #x ";" NEW_LINE
919  #define GNU_AS2(x, y) #x ", " #y ";" NEW_LINE
920  #define GNU_AS3(x, y, z) #x ", " #y ", " #z ";" NEW_LINE
921  #define GNU_ASL(x) "\n" #x ":" NEW_LINE
922 // clang 5.0.0 and apple clang 9.0.0 don't support numerical backward jumps
923 #if (CRYPTOPP_LLVM_CLANG_VERSION >= 50000) || (CRYPTOPP_APPLE_CLANG_VERSION >= 90000)
924  #define GNU_ASJ(x, y, z) ATT_PREFIX ";" NEW_LINE #x " " #y #z ";" NEW_LINE INTEL_PREFIX ";" NEW_LINE
925 #else
926  #define GNU_ASJ(x, y, z) #x " " #y #z ";" NEW_LINE
927 #endif
928  #define AS1(x) GNU_AS1(x)
929  #define AS2(x, y) GNU_AS2(x, y)
930  #define AS3(x, y, z) GNU_AS3(x, y, z)
931  #define ASS(x, y, a, b, c, d) #x ", " #y ", " #a "*64+" #b "*16+" #c "*4+" #d ";"
932  #define ASL(x) GNU_ASL(x)
933  #define ASJ(x, y, z) GNU_ASJ(x, y, z)
934  #define ASC(x, y) #x " " #y ";"
935  #define CRYPTOPP_NAKED
936  #define AS_HEX(y) 0x##y
937 #endif
938 
939 #define IF0(y)
940 #define IF1(y) y
941 
942 #ifdef CRYPTOPP_GENERATE_X64_MASM
943 #define ASM_MOD(x, y) ((x) MOD (y))
944 #define XMMWORD_PTR XMMWORD PTR
945 #else
946 // GNU assembler doesn't seem to have mod operator
947 #define ASM_MOD(x, y) ((x)-((x)/(y))*(y))
948 // GAS 2.15 doesn't support XMMWORD PTR. it seems necessary only for MASM
949 #define XMMWORD_PTR
950 #endif
951 
952 #if CRYPTOPP_BOOL_X86
953  #define AS_REG_1 ecx
954  #define AS_REG_2 edx
955  #define AS_REG_3 esi
956  #define AS_REG_4 edi
957  #define AS_REG_5 eax
958  #define AS_REG_6 ebx
959  #define AS_REG_7 ebp
960  #define AS_REG_1d ecx
961  #define AS_REG_2d edx
962  #define AS_REG_3d esi
963  #define AS_REG_4d edi
964  #define AS_REG_5d eax
965  #define AS_REG_6d ebx
966  #define AS_REG_7d ebp
967  #define WORD_SZ 4
968  #define WORD_REG(x) e##x
969  #define WORD_PTR DWORD PTR
970  #define AS_PUSH_IF86(x) AS1(push e##x)
971  #define AS_POP_IF86(x) AS1(pop e##x)
972  #define AS_JCXZ jecxz
973 #elif CRYPTOPP_BOOL_X32
974  #define AS_REG_1 ecx
975  #define AS_REG_2 edx
976  #define AS_REG_3 r8d
977  #define AS_REG_4 r9d
978  #define AS_REG_5 eax
979  #define AS_REG_6 r10d
980  #define AS_REG_7 r11d
981  #define AS_REG_1d ecx
982  #define AS_REG_2d edx
983  #define AS_REG_3d r8d
984  #define AS_REG_4d r9d
985  #define AS_REG_5d eax
986  #define AS_REG_6d r10d
987  #define AS_REG_7d r11d
988  #define WORD_SZ 4
989  #define WORD_REG(x) e##x
990  #define WORD_PTR DWORD PTR
991  #define AS_PUSH_IF86(x) AS1(push r##x)
992  #define AS_POP_IF86(x) AS1(pop r##x)
993  #define AS_JCXZ jecxz
994 #elif CRYPTOPP_BOOL_X64
995  #ifdef CRYPTOPP_GENERATE_X64_MASM
996  #define AS_REG_1 rcx
997  #define AS_REG_2 rdx
998  #define AS_REG_3 r8
999  #define AS_REG_4 r9
1000  #define AS_REG_5 rax
1001  #define AS_REG_6 r10
1002  #define AS_REG_7 r11
1003  #define AS_REG_1d ecx
1004  #define AS_REG_2d edx
1005  #define AS_REG_3d r8d
1006  #define AS_REG_4d r9d
1007  #define AS_REG_5d eax
1008  #define AS_REG_6d r10d
1009  #define AS_REG_7d r11d
1010  #else
1011  #define AS_REG_1 rdi
1012  #define AS_REG_2 rsi
1013  #define AS_REG_3 rdx
1014  #define AS_REG_4 rcx
1015  #define AS_REG_5 r8
1016  #define AS_REG_6 r9
1017  #define AS_REG_7 r10
1018  #define AS_REG_1d edi
1019  #define AS_REG_2d esi
1020  #define AS_REG_3d edx
1021  #define AS_REG_4d ecx
1022  #define AS_REG_5d r8d
1023  #define AS_REG_6d r9d
1024  #define AS_REG_7d r10d
1025  #endif
1026  #define WORD_SZ 8
1027  #define WORD_REG(x) r##x
1028  #define WORD_PTR QWORD PTR
1029  #define AS_PUSH_IF86(x)
1030  #define AS_POP_IF86(x)
1031  #define AS_JCXZ jrcxz
1032 #endif
1033 
1034 // helper macro for stream cipher output
1035 #define AS_XMM_OUTPUT4(labelPrefix, inputPtr, outputPtr, x0, x1, x2, x3, t, p0, p1, p2, p3, increment)\
1036  AS2( test inputPtr, inputPtr)\
1037  ASC( jz, labelPrefix##3)\
1038  AS2( test inputPtr, 15)\
1039  ASC( jnz, labelPrefix##7)\
1040  AS2( pxor xmm##x0, [inputPtr+p0*16])\
1041  AS2( pxor xmm##x1, [inputPtr+p1*16])\
1042  AS2( pxor xmm##x2, [inputPtr+p2*16])\
1043  AS2( pxor xmm##x3, [inputPtr+p3*16])\
1044  AS2( add inputPtr, increment*16)\
1045  ASC( jmp, labelPrefix##3)\
1046  ASL(labelPrefix##7)\
1047  AS2( movdqu xmm##t, [inputPtr+p0*16])\
1048  AS2( pxor xmm##x0, xmm##t)\
1049  AS2( movdqu xmm##t, [inputPtr+p1*16])\
1050  AS2( pxor xmm##x1, xmm##t)\
1051  AS2( movdqu xmm##t, [inputPtr+p2*16])\
1052  AS2( pxor xmm##x2, xmm##t)\
1053  AS2( movdqu xmm##t, [inputPtr+p3*16])\
1054  AS2( pxor xmm##x3, xmm##t)\
1055  AS2( add inputPtr, increment*16)\
1056  ASL(labelPrefix##3)\
1057  AS2( test outputPtr, 15)\
1058  ASC( jnz, labelPrefix##8)\
1059  AS2( movdqa [outputPtr+p0*16], xmm##x0)\
1060  AS2( movdqa [outputPtr+p1*16], xmm##x1)\
1061  AS2( movdqa [outputPtr+p2*16], xmm##x2)\
1062  AS2( movdqa [outputPtr+p3*16], xmm##x3)\
1063  ASC( jmp, labelPrefix##9)\
1064  ASL(labelPrefix##8)\
1065  AS2( movdqu [outputPtr+p0*16], xmm##x0)\
1066  AS2( movdqu [outputPtr+p1*16], xmm##x1)\
1067  AS2( movdqu [outputPtr+p2*16], xmm##x2)\
1068  AS2( movdqu [outputPtr+p3*16], xmm##x3)\
1069  ASL(labelPrefix##9)\
1070  AS2( add outputPtr, increment*16)
1071 
1072 #endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
1073 
1074 #endif // Not CRYPTOPP_DOXYGEN_PROCESSING
1075 
1076 NAMESPACE_END
1077 
1078 // Issue 340
1079 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
1080 # pragma GCC diagnostic pop
1081 #endif
1082 
1083 #endif // CRYPTOPP_CPU_H
bool HasSHA()
Determine SHA availability.
Definition: cpu.h:227
bool HasDARN()
Determine if a PowerPC processor has DARN available.
Definition: cpu.h:836
bool HasAltivec()
Determine if a PowerPC processor has Altivec available.
Definition: cpu.h:696
bool HasSM4()
Determine if an ARM processor has SM4 available.
Definition: cpu.h:651
bool HasCRC32()
Determine if an ARM processor has CRC32 available.
Definition: cpu.h:511
bool HasSSSE3()
Determine SSSE3 availability.
Definition: cpu.h:133
bool HasADX()
Determine ADX availability.
Definition: cpu.h:243
bool HasPadlockRNG()
Determine Padlock RNG availability.
Definition: cpu.h:320
bool HasAVX2()
Determine AVX2 availability.
Definition: cpu.h:275
bool HasAES()
Determine if an ARM processor has AES available.
Definition: cpu.h:531
bool IsP4()
Determine if the CPU is an Intel P4.
Definition: cpu.h:395
Library configuration file.
int GetCacheLineSize()
Provides the cache line size.
Definition: cpu.h:410
bool HasRDRAND()
Determine RDRAND availability.
Definition: cpu.h:290
bool HasPower7()
Determine if a PowerPC processor has Power7 available.
Definition: cpu.h:713
bool HasSHA256()
Determine if a PowerPC processor has SHA256 available.
Definition: cpu.h:801
bool HasSM3()
Determine if an ARM processor has SM3 available.
Definition: cpu.h:631
bool HasPower8()
Determine if a PowerPC processor has Power8 available.
Definition: cpu.h:730
bool HasRDSEED()
Determine RDSEED availability.
Definition: cpu.h:305
bool HasCLMUL()
Determine Carryless Multiply availability.
Definition: cpu.h:211
bool HasSHA1()
Determine if an ARM processor has SHA1 available.
Definition: cpu.h:551
bool HasSHA512()
Determine if an ARM processor has SHA512 available.
Definition: cpu.h:591
bool HasPadlockACE2()
Determine Padlock ACE2 availability.
Definition: cpu.h:350
bool HasPadlockPHE()
Determine Padlock PHE availability.
Definition: cpu.h:365
bool HasMOVBE()
Determine MOVBE availability.
Definition: cpu.h:179
bool HasPadlockPMM()
Determine Padlock PMM availability.
Definition: cpu.h:380
bool HasAESNI()
Determine AES-NI availability.
Definition: cpu.h:195
bool HasPower9()
Determine if a PowerPC processor has Power9 available.
Definition: cpu.h:747
bool HasSSE2()
Determine SSE2 availability.
Definition: cpu.h:118
bool HasSHA2()
Determine if an ARM processor has SHA256 available.
Definition: cpu.h:571
bool HasAVX()
Determine AVX availability.
Definition: cpu.h:259
bool HasSSE41()
Determine SSE4.1 availability.
Definition: cpu.h:148
Crypto++ library namespace.
bool HasSHA3()
Determine if an ARM processor has SHA3 available.
Definition: cpu.h:611
bool HasARMv7()
Determine if an ARM processor is ARMv7 or above.
Definition: cpu.h:449
bool HasPadlockACE()
Determine Padlock ACE availability.
Definition: cpu.h:335
bool HasSSE42()
Determine SSE4.2 availability.
Definition: cpu.h:163
bool HasPMULL()
Determine if an ARM processor provides Polynomial Multiplication.
Definition: cpu.h:490
bool HasNEON()
Determine if an ARM processor has Advanced SIMD available.
Definition: cpu.h:469