Crypto++  5.6.3
Free C++ class library of cryptographic schemes
cpu.h
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1 // cpu.h - written and placed in the public domain by Wei Dai
2 
3 //! \file cpu.h
4 //! \brief Functions for CPU features and intrinsics
5 //! \details The functions are used in X86/X32/X64 and NEON code paths
6 
7 #ifndef CRYPTOPP_CPU_H
8 #define CRYPTOPP_CPU_H
9 
10 #include "config.h"
11 
12 // ARM32/ARM64 includes
13 #if (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
14 # if defined(__GNUC__)
15 # include <stdint.h>
16 # endif
17 # if CRYPTOPP_BOOL_NEON_INTRINSICS_AVAILABLE || defined(__ARM_NEON)
18 # include <arm_neon.h>
19 # endif
20 # if (CRYPTOPP_BOOL_ARM_CRYPTO_INTRINSICS_AVAILABLE || CRYPTOPP_BOOL_ARM_CRC32_INTRINSICS_AVAILABLE) || defined(__ARM_ACLE)
21 # include <arm_acle.h>
22 # endif
23 #endif // ARM32 and ARM64
24 
25 // Applies to both X86/X32/X64 and ARM32/ARM64. And we've got MIPS devices on the way.
26 #if defined(_MSC_VER) || defined(__BORLANDC__)
27 # define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
28 #else
29 # define CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
30 #endif
31 
32 // Applies to both X86/X32/X64 and ARM32/ARM64
33 #if defined(CRYPTOPP_LLVM_CLANG_VERSION) || defined(CRYPTOPP_APPLE_CLANG_VERSION) || defined(CRYPTOPP_CLANG_INTEGRATED_ASSEMBLER)
34  #define NEW_LINE "\n"
35  #define INTEL_PREFIX ".intel_syntax;"
36  #define INTEL_NOPREFIX ".intel_syntax;"
37  #define ATT_PREFIX ".att_syntax;"
38  #define ATT_NOPREFIX ".att_syntax;"
39 #elif defined(__GNUC__)
40  #define NEW_LINE
41  #define INTEL_PREFIX ".intel_syntax prefix;"
42  #define INTEL_NOPREFIX ".intel_syntax noprefix;"
43  #define ATT_PREFIX ".att_syntax prefix;"
44  #define ATT_NOPREFIX ".att_syntax noprefix;"
45 #else
46  #define NEW_LINE
47  #define INTEL_PREFIX
48  #define INTEL_NOPREFIX
49  #define ATT_PREFIX
50  #define ATT_NOPREFIX
51 #endif
52 
53 #ifdef CRYPTOPP_GENERATE_X64_MASM
54 
55 #define CRYPTOPP_X86_ASM_AVAILABLE
56 #define CRYPTOPP_BOOL_X64 1
57 #define CRYPTOPP_BOOL_SSE2_ASM_AVAILABLE 1
58 #define NAMESPACE_END
59 
60 #else
61 
62 # if CRYPTOPP_BOOL_SSE2_INTRINSICS_AVAILABLE
63 # include <emmintrin.h>
64 # endif
65 
66 #if CRYPTOPP_BOOL_AESNI_INTRINSICS_AVAILABLE
67 
68 // GCC 5.3/i686 fails to declare __m128 in the headers we use when compiling with -std=c++11 or -std=c++14.
69 // Consequently, our _mm_shuffle_epi8, _mm_extract_epi32, etc fails to compile.
70 #if defined(__has_include)
71 # if __has_include(<xmmintrin.h>)
72 # include <xmmintrin.h>
73 # endif
74 #endif
75 
76 // PUSHFB needs Clang 3.3 and Apple Clang 5.0.
77 #if !defined(__GNUC__) || defined(__SSSE3__)|| defined(__INTEL_COMPILER) || (CRYPTOPP_LLVM_CLANG_VERSION >= 30300) || (CRYPTOPP_APPLE_CLANG_VERSION >= 50000)
78 #include <tmmintrin.h>
79 #else
80 NAMESPACE_BEGIN(CryptoPP)
81 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
82 _mm_shuffle_epi8 (__m128i a, __m128i b)
83 {
84  asm ("pshufb %1, %0" : "+x"(a) : "xm"(b));
85  return a;
86 }
87 NAMESPACE_END
88 #endif // tmmintrin.h
89 
90 // PEXTRD needs Clang 3.3 and Apple Clang 5.0.
91 #if !defined(__GNUC__) || defined(__SSE4_1__)|| defined(__INTEL_COMPILER) || (CRYPTOPP_LLVM_CLANG_VERSION >= 30300) || (CRYPTOPP_APPLE_CLANG_VERSION >= 50000)
92 #include <smmintrin.h>
93 #else
94 NAMESPACE_BEGIN(CryptoPP)
95 __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
96 _mm_extract_epi32 (__m128i a, const int i)
97 {
98  int r;
99  asm ("pextrd %2, %1, %0" : "=rm"(r) : "x"(a), "i"(i));
100  return r;
101 }
102 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
103 _mm_insert_epi32 (__m128i a, int b, const int i)
104 {
105  asm ("pinsrd %2, %1, %0" : "+x"(a) : "rm"(b), "i"(i));
106  return a;
107 }
108 NAMESPACE_END
109 #endif // smmintrin.h
110 
111 // AES needs Clang 2.8 and Apple Clang 4.6. PCLMUL needs Clang 3.4 and Apple Clang 6.0
112 #if !defined(__GNUC__) || (defined(__AES__) && defined(__PCLMUL__)) || defined(__INTEL_COMPILER) || (CRYPTOPP_LLVM_CLANG_VERSION >= 30400) || (CRYPTOPP_APPLE_CLANG_VERSION >= 60000)
113 #include <wmmintrin.h>
114 #else
115 NAMESPACE_BEGIN(CryptoPP)
116 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
117 _mm_clmulepi64_si128 (__m128i a, __m128i b, const int i)
118 {
119  asm ("pclmulqdq %2, %1, %0" : "+x"(a) : "xm"(b), "i"(i));
120  return a;
121 }
122 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
123 _mm_aeskeygenassist_si128 (__m128i a, const int i)
124 {
125  __m128i r;
126  asm ("aeskeygenassist %2, %1, %0" : "=x"(r) : "xm"(a), "i"(i));
127  return r;
128 }
129 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
130 _mm_aesimc_si128 (__m128i a)
131 {
132  __m128i r;
133  asm ("aesimc %1, %0" : "=x"(r) : "xm"(a));
134  return r;
135 }
136 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
137 _mm_aesenc_si128 (__m128i a, __m128i b)
138 {
139  asm ("aesenc %1, %0" : "+x"(a) : "xm"(b));
140  return a;
141 }
142 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
143 _mm_aesenclast_si128 (__m128i a, __m128i b)
144 {
145  asm ("aesenclast %1, %0" : "+x"(a) : "xm"(b));
146  return a;
147 }
148 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
149 _mm_aesdec_si128 (__m128i a, __m128i b)
150 {
151  asm ("aesdec %1, %0" : "+x"(a) : "xm"(b));
152  return a;
153 }
154 __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
155 _mm_aesdeclast_si128 (__m128i a, __m128i b)
156 {
157  asm ("aesdeclast %1, %0" : "+x"(a) : "xm"(b));
158  return a;
159 }
160 NAMESPACE_END
161 #endif // wmmintrin.h
162 #endif // CRYPTOPP_BOOL_AESNI_INTRINSICS_AVAILABLE
163 
164 #if (CRYPTOPP_BOOL_SSE4_INTRINSICS_AVAILABLE) && ((__SUNPRO_CC >= 0x5110) || defined(__clang__) || defined(__INTEL_COMPILER))
165 # include <emmintrin.h> // _mm_set_epi64x
166 # include <smmintrin.h> // _mm_blend_epi16
167 # include <tmmintrin.h> // _mm_shuffle_epi16
168 # include <nmmintrin.h> // _mm_crc32_u{8|16|32}
169 #endif
170 
171 NAMESPACE_BEGIN(CryptoPP)
172 
173 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
174 
175 #define CRYPTOPP_CPUID_AVAILABLE
176 
177 // Hide from Doxygen
178 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
179 // These should not be used directly
180 extern CRYPTOPP_DLL bool g_x86DetectionDone;
181 extern CRYPTOPP_DLL bool g_hasMMX;
182 extern CRYPTOPP_DLL bool g_hasISSE;
183 extern CRYPTOPP_DLL bool g_hasSSE2;
184 extern CRYPTOPP_DLL bool g_hasSSSE3;
185 extern CRYPTOPP_DLL bool g_hasSSE4;
186 extern CRYPTOPP_DLL bool g_hasAESNI;
187 extern CRYPTOPP_DLL bool g_hasCLMUL;
188 extern CRYPTOPP_DLL bool g_isP4;
189 extern CRYPTOPP_DLL bool g_hasRDRAND;
190 extern CRYPTOPP_DLL bool g_hasRDSEED;
191 extern CRYPTOPP_DLL bool g_hasPadlockRNG;
192 extern CRYPTOPP_DLL bool g_hasPadlockACE;
193 extern CRYPTOPP_DLL bool g_hasPadlockACE2;
194 extern CRYPTOPP_DLL bool g_hasPadlockPHE;
195 extern CRYPTOPP_DLL bool g_hasPadlockPMM;
196 extern CRYPTOPP_DLL word32 g_cacheLineSize;
197 
198 CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
199 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 input, word32 output[4]);
200 #endif // CRYPTOPP_DOXYGEN_PROCESSING
201 
202 //! \brief Determines MMX availability
203 //! \returns true if MMX is determined to be available, false otherwise
204 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
205 //! the function always returns true for the platform.
206 inline bool HasMMX()
207 {
208 #if CRYPTOPP_BOOL_X64
209  return true;
210 #else
211  if (!g_x86DetectionDone)
212  DetectX86Features();
213  return g_hasMMX;
214 #endif
215 }
216 
217 //! \brief Determines SSE availability
218 //! \returns true if SSE is determined to be available, false otherwise
219 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
220 //! the function always returns true for the platform.
221 inline bool HasISSE()
222 {
223 #if CRYPTOPP_BOOL_X64
224  return true;
225 #else
226  if (!g_x86DetectionDone)
227  DetectX86Features();
228  return g_hasISSE;
229 #endif
230 }
231 
232 //! \brief Determines SSE2 availability
233 //! \returns true if SSE2 is determined to be available, false otherwise
234 //! \details MMX, SSE and SSE2 are core processor features for x86_64, and
235 //! the function always returns true for the platform.
236 inline bool HasSSE2()
237 {
238 #if CRYPTOPP_BOOL_X64
239  return true;
240 #else
241  if (!g_x86DetectionDone)
242  DetectX86Features();
243  return g_hasSSE2;
244 #endif
245 }
246 
247 //! \brief Determines SSSE3 availability
248 //! \returns true if SSSE3 is determined to be available, false otherwise
249 //! \details HasSSSE3() is a runtime check performed using CPUID
250 //! \note Some Clang compilers incorrectly omit SSSE3 even though its native to the processor.
251 inline bool HasSSSE3()
252 {
253  if (!g_x86DetectionDone)
254  DetectX86Features();
255  return g_hasSSSE3;
256 }
257 
258 //! \brief Determines SSE4 availability
259 //! \returns true if SSE4.1 and SSE4.2 are determined to be available, false otherwise
260 //! \details HasSSE4() is a runtime check performed using CPUID which requires both SSE4.1 and SSE4.2
261 inline bool HasSSE4()
262 {
263  if (!g_x86DetectionDone)
264  DetectX86Features();
265  return g_hasSSE4;
266 }
267 
268 //! \brief Determines AES-NI availability
269 //! \returns true if AES-NI is determined to be available, false otherwise
270 //! \details HasAESNI() is a runtime check performed using CPUID
271 inline bool HasAESNI()
272 {
273  if (!g_x86DetectionDone)
274  DetectX86Features();
275  return g_hasAESNI;
276 }
277 
278 //! \brief Determines Carryless Multiply availability
279 //! \returns true if pclmulqdq is determined to be available, false otherwise
280 //! \details HasCLMUL() is a runtime check performed using CPUID
281 inline bool HasCLMUL()
282 {
283  if (!g_x86DetectionDone)
284  DetectX86Features();
285  return g_hasCLMUL;
286 }
287 
288 //! \brief Determines if the CPU is an Intel P4
289 //! \returns true if the CPU is a P4, false otherwise
290 //! \details IsP4() is a runtime check performed using CPUID
291 inline bool IsP4()
292 {
293  if (!g_x86DetectionDone)
294  DetectX86Features();
295  return g_isP4;
296 }
297 
298 //! \brief Determines RDRAND availability
299 //! \returns true if RDRAND is determined to be available, false otherwise
300 //! \details HasRDRAND() is a runtime check performed using CPUID
301 inline bool HasRDRAND()
302 {
303  if (!g_x86DetectionDone)
304  DetectX86Features();
305  return g_hasRDRAND;
306 }
307 
308 //! \brief Determines RDSEED availability
309 //! \returns true if RDSEED is determined to be available, false otherwise
310 //! \details HasRDSEED() is a runtime check performed using CPUID
311 inline bool HasRDSEED()
312 {
313  if (!g_x86DetectionDone)
314  DetectX86Features();
315  return g_hasRDSEED;
316 }
317 
318 //! \brief Determines Padlock RNG availability
319 //! \returns true if VIA Padlock RNG is determined to be available, false otherwise
320 //! \details HasPadlockRNG() is a runtime check performed using CPUID
321 inline bool HasPadlockRNG()
322 {
323  if (!g_x86DetectionDone)
324  DetectX86Features();
325  return g_hasPadlockRNG;
326 }
327 
328 //! \brief Determines Padlock ACE availability
329 //! \returns true if VIA Padlock ACE is determined to be available, false otherwise
330 //! \details HasPadlockACE() is a runtime check performed using CPUID
331 inline bool HasPadlockACE()
332 {
333  if (!g_x86DetectionDone)
334  DetectX86Features();
335  return g_hasPadlockACE;
336 }
337 
338 //! \brief Determines Padlock ACE2 availability
339 //! \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
340 //! \details HasPadlockACE2() is a runtime check performed using CPUID
341 inline bool HasPadlockACE2()
342 {
343  if (!g_x86DetectionDone)
344  DetectX86Features();
345  return g_hasPadlockACE2;
346 }
347 
348 //! \brief Determines Padlock PHE availability
349 //! \returns true if VIA Padlock PHE is determined to be available, false otherwise
350 //! \details HasPadlockPHE() is a runtime check performed using CPUID
351 inline bool HasPadlockPHE()
352 {
353  if (!g_x86DetectionDone)
354  DetectX86Features();
355  return g_hasPadlockPHE;
356 }
357 
358 //! \brief Determines Padlock PMM availability
359 //! \returns true if VIA Padlock PMM is determined to be available, false otherwise
360 //! \details HasPadlockPMM() is a runtime check performed using CPUID
361 inline bool HasPadlockPMM()
362 {
363  if (!g_x86DetectionDone)
364  DetectX86Features();
365  return g_hasPadlockPMM;
366 }
367 
368 //! \brief Provides the cache line size
369 //! \returns lower bound on the size of a cache line in bytes, if available
370 //! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
371 //! is available. If the value is not available at runtime, then 32 is returned for a 32-bit
372 //! processor and 64 is returned for a 64-bit processor.
373 //! \details x86/x32/x64 uses CPUID to determine the value and its usually accurate. The ARM
374 //! processor equivalent is a privileged instruction, so a compile time value is returned.
375 inline int GetCacheLineSize()
376 {
377  if (!g_x86DetectionDone)
378  DetectX86Features();
379  return g_cacheLineSize;
380 }
381 
382 #elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
383 
384 extern bool g_ArmDetectionDone;
385 extern bool g_hasNEON, g_hasPMULL, g_hasCRC32, g_hasAES, g_hasSHA1, g_hasSHA2;
386 void CRYPTOPP_API DetectArmFeatures();
387 
388 //! \brief Determine if an ARM processor has Advanced SIMD available
389 //! \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
390 //! \details Advanced SIMD instructions are available under Aarch64 (ARM-64) and Aarch32 (ARM-32).
391 //! \details Runtime support requires compile time support. When compiling with GCC, you may
392 //! need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>
393 //! (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.
394 inline bool HasNEON()
395 {
396  if (!g_ArmDetectionDone)
397  DetectArmFeatures();
398  return g_hasNEON;
399 }
400 
401 //! \brief Determine if an ARM processor provides Polynomial Multiplication (long)
402 //! \returns true if the hardware is capable of polynomial multiplications at runtime, false otherwise.
403 //! \details The multiplication instructions are available under Aarch64 (ARM-64) and Aarch32 (ARM-32).
404 //! \details Runtime support requires compile time support. When compiling with GCC, you may
405 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
406 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
407 inline bool HasPMULL()
408 {
409  if (!g_ArmDetectionDone)
410  DetectArmFeatures();
411  return g_hasPMULL;
412 }
413 
414 //! \brief Determine if an ARM processor has CRC32 available
415 //! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
416 //! \details CRC32 instructions provide access to the processor's CRC32 and CRC32-C intructions.
417 //! They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and available under Aarch64
418 //! (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an AArch32 execution environment).
419 //! \details Runtime support requires compile time support. When compiling with GCC, you may
420 //! need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires
421 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.
422 inline bool HasCRC32()
423 {
424  if (!g_ArmDetectionDone)
425  DetectArmFeatures();
426  return g_hasCRC32;
427 }
428 
429 //! \brief Determine if an ARM processor has AES available
430 //! \returns true if the hardware is capable of AES at runtime, false otherwise.
431 //! \details AES is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
432 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
433 //! AArch32 execution environment).
434 //! \details Runtime support requires compile time support. When compiling with GCC, you may
435 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
436 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
437 inline bool HasAES()
438 {
439  if (!g_ArmDetectionDone)
440  DetectArmFeatures();
441  return g_hasAES;
442 }
443 
444 //! \brief Determine if an ARM processor has SHA1 available
445 //! \returns true if the hardware is capable of SHA1 at runtime, false otherwise.
446 //! \details SHA1 is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
447 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
448 //! AArch32 execution environment).
449 //! \details Runtime support requires compile time support. When compiling with GCC, you may
450 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
451 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
452 inline bool HasSHA1()
453 {
454  if (!g_ArmDetectionDone)
455  DetectArmFeatures();
456  return g_hasSHA1;
457 }
458 
459 //! \brief Determine if an ARM processor has SHA2 available
460 //! \returns true if the hardware is capable of SHA2 at runtime, false otherwise.
461 //! \details SHA2 is part of the Crypto extensions from ARM C Language Extensions 2.0 (ACLE 2.0)
462 //! and available under Aarch64 (ARM-64) and Aarch32 (ARM-32) running on Aarch64 (i.e., an
463 //! AArch32 execution environment).
464 //! \details Runtime support requires compile time support. When compiling with GCC, you may
465 //! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
466 //! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
467 inline bool HasSHA2()
468 {
469  if (!g_ArmDetectionDone)
470  DetectArmFeatures();
471  return g_hasSHA2;
472 }
473 
474 //! \brief Provides the cache line size at runtime
475 //! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
476 //! \details GetCacheLineSize() provides is an estimate using CRYPTOPP_L1_CACHE_LINE_SIZE.
477 //! The runtime instructions to query the processor are privileged.
478 inline int GetCacheLineSize()
479 {
480  return CRYPTOPP_L1_CACHE_LINE_SIZE;
481 }
482 
483 #else
484 
485 inline int GetCacheLineSize()
486 {
487  return CRYPTOPP_L1_CACHE_LINE_SIZE;
488 }
489 
490 #endif // X86/X32/X64 and ARM
491 
492 #endif
493 
494 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
495 
496 #ifdef CRYPTOPP_GENERATE_X64_MASM
497  #define AS1(x) x*newline*
498  #define AS2(x, y) x, y*newline*
499  #define AS3(x, y, z) x, y, z*newline*
500  #define ASS(x, y, a, b, c, d) x, y, a*64+b*16+c*4+d*newline*
501  #define ASL(x) label##x:*newline*
502  #define ASJ(x, y, z) x label##y*newline*
503  #define ASC(x, y) x label##y*newline*
504  #define AS_HEX(y) 0##y##h
505 #elif defined(_MSC_VER) || defined(__BORLANDC__)
506  #define CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
507  #define AS1(x) __asm {x}
508  #define AS2(x, y) __asm {x, y}
509  #define AS3(x, y, z) __asm {x, y, z}
510  #define ASS(x, y, a, b, c, d) __asm {x, y, (a)*64+(b)*16+(c)*4+(d)}
511  #define ASL(x) __asm {label##x:}
512  #define ASJ(x, y, z) __asm {x label##y}
513  #define ASC(x, y) __asm {x label##y}
514  #define CRYPTOPP_NAKED __declspec(naked)
515  #define AS_HEX(y) 0x##y
516 #else
517  #define CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
518 
519  // define these in two steps to allow arguments to be expanded
520  #define GNU_AS1(x) #x ";" NEW_LINE
521  #define GNU_AS2(x, y) #x ", " #y ";" NEW_LINE
522  #define GNU_AS3(x, y, z) #x ", " #y ", " #z ";" NEW_LINE
523  #define GNU_ASL(x) "\n" #x ":" NEW_LINE
524  #define GNU_ASJ(x, y, z) #x " " #y #z ";" NEW_LINE
525  #define AS1(x) GNU_AS1(x)
526  #define AS2(x, y) GNU_AS2(x, y)
527  #define AS3(x, y, z) GNU_AS3(x, y, z)
528  #define ASS(x, y, a, b, c, d) #x ", " #y ", " #a "*64+" #b "*16+" #c "*4+" #d ";"
529  #define ASL(x) GNU_ASL(x)
530  #define ASJ(x, y, z) GNU_ASJ(x, y, z)
531  #define ASC(x, y) #x " " #y ";"
532  #define CRYPTOPP_NAKED
533  #define AS_HEX(y) 0x##y
534 #endif
535 
536 #define IF0(y)
537 #define IF1(y) y
538 
539 #ifdef CRYPTOPP_GENERATE_X64_MASM
540 #define ASM_MOD(x, y) ((x) MOD (y))
541 #define XMMWORD_PTR XMMWORD PTR
542 #else
543 // GNU assembler doesn't seem to have mod operator
544 #define ASM_MOD(x, y) ((x)-((x)/(y))*(y))
545 // GAS 2.15 doesn't support XMMWORD PTR. it seems necessary only for MASM
546 #define XMMWORD_PTR
547 #endif
548 
549 #if CRYPTOPP_BOOL_X86
550  #define AS_REG_1 ecx
551  #define AS_REG_2 edx
552  #define AS_REG_3 esi
553  #define AS_REG_4 edi
554  #define AS_REG_5 eax
555  #define AS_REG_6 ebx
556  #define AS_REG_7 ebp
557  #define AS_REG_1d ecx
558  #define AS_REG_2d edx
559  #define AS_REG_3d esi
560  #define AS_REG_4d edi
561  #define AS_REG_5d eax
562  #define AS_REG_6d ebx
563  #define AS_REG_7d ebp
564  #define WORD_SZ 4
565  #define WORD_REG(x) e##x
566  #define WORD_PTR DWORD PTR
567  #define AS_PUSH_IF86(x) AS1(push e##x)
568  #define AS_POP_IF86(x) AS1(pop e##x)
569  #define AS_JCXZ jecxz
570 #elif CRYPTOPP_BOOL_X32
571  #define AS_REG_1 ecx
572  #define AS_REG_2 edx
573  #define AS_REG_3 r8d
574  #define AS_REG_4 r9d
575  #define AS_REG_5 eax
576  #define AS_REG_6 r10d
577  #define AS_REG_7 r11d
578  #define AS_REG_1d ecx
579  #define AS_REG_2d edx
580  #define AS_REG_3d r8d
581  #define AS_REG_4d r9d
582  #define AS_REG_5d eax
583  #define AS_REG_6d r10d
584  #define AS_REG_7d r11d
585  #define WORD_SZ 4
586  #define WORD_REG(x) e##x
587  #define WORD_PTR DWORD PTR
588  #define AS_PUSH_IF86(x) AS1(push r##x)
589  #define AS_POP_IF86(x) AS1(pop r##x)
590  #define AS_JCXZ jecxz
591 #elif CRYPTOPP_BOOL_X64
592  #ifdef CRYPTOPP_GENERATE_X64_MASM
593  #define AS_REG_1 rcx
594  #define AS_REG_2 rdx
595  #define AS_REG_3 r8
596  #define AS_REG_4 r9
597  #define AS_REG_5 rax
598  #define AS_REG_6 r10
599  #define AS_REG_7 r11
600  #define AS_REG_1d ecx
601  #define AS_REG_2d edx
602  #define AS_REG_3d r8d
603  #define AS_REG_4d r9d
604  #define AS_REG_5d eax
605  #define AS_REG_6d r10d
606  #define AS_REG_7d r11d
607  #else
608  #define AS_REG_1 rdi
609  #define AS_REG_2 rsi
610  #define AS_REG_3 rdx
611  #define AS_REG_4 rcx
612  #define AS_REG_5 r8
613  #define AS_REG_6 r9
614  #define AS_REG_7 r10
615  #define AS_REG_1d edi
616  #define AS_REG_2d esi
617  #define AS_REG_3d edx
618  #define AS_REG_4d ecx
619  #define AS_REG_5d r8d
620  #define AS_REG_6d r9d
621  #define AS_REG_7d r10d
622  #endif
623  #define WORD_SZ 8
624  #define WORD_REG(x) r##x
625  #define WORD_PTR QWORD PTR
626  #define AS_PUSH_IF86(x)
627  #define AS_POP_IF86(x)
628  #define AS_JCXZ jrcxz
629 #endif
630 
631 // helper macro for stream cipher output
632 #define AS_XMM_OUTPUT4(labelPrefix, inputPtr, outputPtr, x0, x1, x2, x3, t, p0, p1, p2, p3, increment)\
633  AS2( test inputPtr, inputPtr)\
634  ASC( jz, labelPrefix##3)\
635  AS2( test inputPtr, 15)\
636  ASC( jnz, labelPrefix##7)\
637  AS2( pxor xmm##x0, [inputPtr+p0*16])\
638  AS2( pxor xmm##x1, [inputPtr+p1*16])\
639  AS2( pxor xmm##x2, [inputPtr+p2*16])\
640  AS2( pxor xmm##x3, [inputPtr+p3*16])\
641  AS2( add inputPtr, increment*16)\
642  ASC( jmp, labelPrefix##3)\
643  ASL(labelPrefix##7)\
644  AS2( movdqu xmm##t, [inputPtr+p0*16])\
645  AS2( pxor xmm##x0, xmm##t)\
646  AS2( movdqu xmm##t, [inputPtr+p1*16])\
647  AS2( pxor xmm##x1, xmm##t)\
648  AS2( movdqu xmm##t, [inputPtr+p2*16])\
649  AS2( pxor xmm##x2, xmm##t)\
650  AS2( movdqu xmm##t, [inputPtr+p3*16])\
651  AS2( pxor xmm##x3, xmm##t)\
652  AS2( add inputPtr, increment*16)\
653  ASL(labelPrefix##3)\
654  AS2( test outputPtr, 15)\
655  ASC( jnz, labelPrefix##8)\
656  AS2( movdqa [outputPtr+p0*16], xmm##x0)\
657  AS2( movdqa [outputPtr+p1*16], xmm##x1)\
658  AS2( movdqa [outputPtr+p2*16], xmm##x2)\
659  AS2( movdqa [outputPtr+p3*16], xmm##x3)\
660  ASC( jmp, labelPrefix##9)\
661  ASL(labelPrefix##8)\
662  AS2( movdqu [outputPtr+p0*16], xmm##x0)\
663  AS2( movdqu [outputPtr+p1*16], xmm##x1)\
664  AS2( movdqu [outputPtr+p2*16], xmm##x2)\
665  AS2( movdqu [outputPtr+p3*16], xmm##x3)\
666  ASL(labelPrefix##9)\
667  AS2( add outputPtr, increment*16)
668 
669 #endif // X86/X32/X64
670 
671 NAMESPACE_END
672 
673 #endif // CRYPTOPP_CPU_H
bool HasISSE()
Determines SSE availability.
Definition: cpu.h:221
bool HasSSE4()
Determines SSE4 availability.
Definition: cpu.h:261
bool HasSSSE3()
Determines SSSE3 availability.
Definition: cpu.h:251
bool HasPadlockRNG()
Determines Padlock RNG availability.
Definition: cpu.h:321
bool IsP4()
Determines if the CPU is an Intel P4.
Definition: cpu.h:291
Library configuration file.
int GetCacheLineSize()
Provides the cache line size.
Definition: cpu.h:375
bool HasRDRAND()
Determines RDRAND availability.
Definition: cpu.h:301
bool HasRDSEED()
Determines RDSEED availability.
Definition: cpu.h:311
bool HasCLMUL()
Determines Carryless Multiply availability.
Definition: cpu.h:281
bool HasPadlockACE2()
Determines Padlock ACE2 availability.
Definition: cpu.h:341
bool HasPadlockPHE()
Determines Padlock PHE availability.
Definition: cpu.h:351
bool HasPadlockPMM()
Determines Padlock PMM availability.
Definition: cpu.h:361
bool HasAESNI()
Determines AES-NI availability.
Definition: cpu.h:271
bool HasSSE2()
Determines SSE2 availability.
Definition: cpu.h:236
bool HasMMX()
Determines MMX availability.
Definition: cpu.h:206
Crypto++ library namespace.
bool HasPadlockACE()
Determines Padlock ACE availability.
Definition: cpu.h:331